© Copyright 1997 ALSE              VHDL Beginner's Corner

VHDL Brain Teaser 3 !  
Find all the Errors
Grade : very easy.

Trouvez les Erreurs !
(très facile)

The VHDL code below exhibits one of the most common design errors.

What to do : Find what's wrong with what was intended as a 4-bit Johnson counter .

Doing the Quiz :

1. Explain in no more than 10 lines of text what is wrong with this design.
2. Fix the source code but try to minimize the changes (don't  switch to signals !).

Note : You can simply cut and paste the text below to try it on your tools.

-- ----------------------------------------------------
--   Johnson Counter, using Variables
--   This design does NOT work as expected !
--   (c) ALSE - B. Cuzeau / VHDL Training
-- ----------------------------------------------------
-- This very simple example demonstrates that using variables
-- is often less obvious than it may appear.
-- Signals are usually a simpler (safer) approach to
-- sequential problems since they follow simpler rules.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity JOHNvar is
     Port ( CLK, RST : In   std_logic;
                   C : Out  std_logic_vector (3 downto 0);
                   TC : Out  std_logic );
end JOHNvar;

----------------------------------------
architecture BEHAVIORAL of JOHNvar is

begin
  process( clk, rst )
  variable Q : std_logic_vector (3 downto 0) := "0000";
  begin
   if (rst = '1') then
       Q := "0000";             -- asynchronous clear
   elsif rising_edge(clk) then
       for i in 3 downto 1 loop -- Q(3) := Q(2);
           Q(i) := Q(i-1);      -- Q(2) := Q(1);
       end loop;                -- Q(1) := Q(0);
       Q(0) := not Q(3);        -- Q(0) := not Q(3);
   end if;

   if Q="1111" then             -- TC = Q(3) & Q(2) & Q(1) & Q(0)
       TC<='1';
   else
       TC<='0';
   end if;

   C <= Q;
end process;

end BEHAVIORAL;
-- -----------------------------------------------------------

Desired Schematic Equivalent :

Hint : (do NOT read this unless you are ready to give up)
Look at the above schematic equivalent of this counter, and keep in mind
that we are dealing with variables here : if you replace the variable Q
with a signal Q, it will work. Look at the comments, and confirm your guess by synthesizing and/or
simulating this design.
© Copyright 1997 ALSE