© Copyright 1997 ALSE                VHDL Beginner's Corner

VHDL Brain Teaser 2 !
Find all the (many) Errors !
Grade : easy / medium)

Trouvez les nombreuses Erreurs !
(facile / moyen)

The VHDL code below exhibits many errors among the most common.

Hints : If you cannot find what's wrong with this code, synthesize it and simulate it using this archive.

1. Understand what the author tried to do.
2. Explain in no more than 10 lines of text what is wrong with  this example.
3. Fix the source code but try to minimize the changes.

--- SyncDet.vhd
-- ------------------------------------------------------------------
-- This example does NOT work as expected by his author !
-- Find out why & fix it.
-- Besides, the design is also very poorly written: fix it !
-- E-mail the solution atn : Bert CUZEAU, info@alse-fr.com
-- © Copyright 1997 ALSE
-- ------------------------------------------------------------------
-- Hints :
-- This design is supposed to catch the binary sequence "110" in DIN
-- The "Sync" output is intended to be combinatorial...
-- "Ovr" goes active after 16 ticks and no Synchro pattern detected.
--
-- Flaws :
--   * Std_logic types would be better...
--   * Many synthesis-related issues
--   * Some simulation issues
--   * Reset issue
--   * Design is "late" catching the sequence
--   * Overflow detection doesn't work at all !
--   * ...
-- ------------------------------------------------------------------
--
entity SYNCDET is
  port ( Clk   : in  bit;
         Reset : in  bit;
         DIN   : in  bit;
         Ovr   : out bit;
         Sync  : out bit );
end SYNCDET;


architecture Bad_Bad_Bad of SYNCDET is

  signal Reg1 : bit;
  signal Reg2 : bit;
  signal Reg3 : bit;
  signal Cnt : integer range 0 to 15;

begin
  process (Clk)
  begin
   if (Reset = '1') then
     Cnt <= 0;
     Ovr <= '0';
   elsif Clk='1' and Clk'event then
     Reg1 <= Din;
     Reg2 <= Reg1;
     Reg3 <= Reg2;
     Cnt <= (Cnt + 1) ; -- increment
     if Cnt = 0 then    -- test for overrun
       Ovr <= '1';
     end if;
     if (Reg3 & Reg2 & Reg1 ) = "110" then
       Sync <= '1';
       Cnt  <= 0;
     else
       Sync <= '0';
     end if;
   end if;
  end process;
end Bad_Bad_Bad;

-- -----------------------------------------------------------