You can find below a few useful tools, free to download.

1. Crimson Editor is a very nice, powerful, and free Editor. VHDL- and Verilog-ready indeed !
    
2. VHDL and Verilog Color-coding for MED, (c) ALSE. MED is a shareware editor, which we used prior to Crimson.
    
3. One-sheet Quick Reference Guide for IEEE Numeric library (c) ALSE.
    
4. VHDL 93 Help file (PC). Found on Internet, source unknown, but quite good.
    
5. CPU_Time : Utility (Tcl) to capture the current Date & Time information (“wall clock time”) from within a VHDL simulation. (c) ALSE, for use with ModelSim. Your batch simulation can record start and end time in the VHDL output. Great also for simulation run-time optimization.
    
6. Complete Sources for a Simple UART in VHDL, (c) ALSE. See our IP page.
    
7. ROM generator : translates directly an Intel-Hex file into Synthesizable Verilog ! (c) ALSE. Written in Tcl/Tk.

Disclaimer : these tools and utilities are for personal use only. ALSE takes no responsibility against any problem which may be the direct or indirect consequence of the use of these tools. Use in a commercial or non-educational conext is prohibited without prior written consent from ALSE.