In this section, we assume you are wanting to use an FPGA that includes a Hardware PCIe block. While it is possible to design PCIe “soft-IPs”, this cannot be true for Gen2 and Gen3, and it’s definitely not a good idea for several other reasons. So we are not offering soft-IPs, just IPs that use the low-level “Hard IPs” that can be found in most modern FPGAs.
FPGAs including PCI Express hard-IPs have been available for a relatively long time. However, it is still surprisingly difficult to use this interface in a project and we keep seeing customers struggling.
We can find several explanations :
- The protocol itself is rich and therefore quite complex
- The concepts behind PCIe are not trivial
- The FPGA’s Hard-IPs are also quite complex and configurable beasts
- The PCIe bandwidth is usually very high, so moving data efficiently is normally an absolute requirement. This typically means using SGDMA engines and serving them adequately.
- The amount of data exchanged is typically very high (for example high-res images at high frame rate).
- The “other side” (often a PC or a processor) has to run a “driver” that talks to the FPGA. And this driver has to be developed while being perfectly aligned with the hardware. And it’s often difficult to find both high-end Hardware and Software specialists available for the project and working together.
- Example Designs, Reference Designs, “Best In Class” designs etc are usually a lost cause and can make you err rather than being helpful.
Forget about Cut & Paste…
“Google programming” (trying to re-use existing code publicly available) won’t cut it.
If you do not really and exhaustively master the subject, you won’t be able to build and debug something which will work reliably and with the performance you expect.
Bespoke ? Way to go !
By experience, the way a given application needs to use the PCI Express interface is typically quite unique : the Generation number, the FPGA family, the number of lanes, the type of transfer, the number of BARs, the presence of ROM, the type of data, the data flow, the software constraints, the memory constraints, etc…
In practice, we have given up the idea of putting a “standard” PCIe IP on the shelf, in favor of a model where we can design an IP that matches exactly the design requirements, while offering it at competitive prices, and even as source code if desired !
We have a good history of projects where we were able to address extremely tough challenges with reasonable efforts. Our know-how combined with the number of projects we have designed are the assurance of a rapid convergence and allow us to propose very fair prices.
We will train you !
The second reason why we can help you efficiently (beyond designing the Interface for you) is that we can train you and make sure you become familiar enough with the PCI Express protocol, with the Hard IP, with our code and with the Driver. And that, consequently, you won’t need us to maintain and iterate your design.
We can even train you before you (or ALSE) start your design. After the training, you can decide whether it’s better to let us design this part or if you want to do it yourself.
Keep in mind that we always try to figure out what is best FOR YOU !
This approach is the only Win-Win solution : you have a working high-performance solution, with our backup, and you will have gained enough competence to be autonomous throughout your project’s life. You end up with the lowest possible cost and the highest gained competence.
Where to start ?
If your project is going to require a PCI Express interface and if you think we might help you, then Contact us (and tick “PCI Express” in the list). We’ll get back to you and send you a list of questions to quickly determinate if we are in the best position to help you.