{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"Aurora 8B\/10B \u003Cabbr title=\"Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc… Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.\"\u003EIP\u003C\/abbr\u003E Core","author_name":"Bertrand Cuzeau","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/Aurora-8b-10b-IP-Core.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/Aurora-8b-10b-IP-Core.html'\u003EAurora 8B\/10B \u003Cabbr title=\"Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc… Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.\"\u003EIP\u003C\/abbr\u003E Core\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EAurora 8B\/10B is an open, lightweight, high-speed, and low latency serial protocol suitable for chip-to-chip, board-to-board and backplane applications using Transceivers. For AMD\/Xilinx users, Aurora 8B\/10B is available through the Xilinx Logicore IP for some FPGA families, but not all (in which case we can help) !  The ALSE Aurora 8B\/10B IP Core makes Aurora 8B\/10B available to all FPGAs (and potentially ASICs), including all Altera FPGAs with transceivers (Cyclone, Arria, Stratix, Agilex (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}