{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"ChipBridge (Chip-To-Chip)","author_name":"Bertrand Cuzeau","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/ChipBridge-Chip-To-Chip-IP.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/ChipBridge-Chip-To-Chip-IP.html'\u003EChipBridge (Chip-To-Chip)\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EThis IP is ideal to control a lot of peripherals from a centralized high-end (Master) FPGA (or ASIC) ! Connecting and controlling peripherals from the Master directly is typically difficult and inefficient : lack of support for 3.3V I\/Os, level translators and ESD protections required, difficulty to modify the main FPGA to adapt to changes in the peripherals, Electrical and Safety concerns, PCB routing, and real estate issues\u2026 \n\nUsing a single transceiver and two pairs of signals, ChipBridge (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}