{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"Designing for Stratix 10 & Agilex FPGAs","author_name":"Bertrand Cuzeau","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/Designing-for-Stratix-10-FPGAs.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/Designing-for-Stratix-10-FPGAs.html'\u003EDesigning for Stratix 10 & Agilex FPGAs\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EThe Intel 14 nm Stratix 10, and even more the newer Intel 10 nm Agilex  FPGA families offer unprecedented performance. \n\nHowever, taking full advantage of these architectures and associated design tools requires to adopt new design techniques and use a new generation of tools. We have the proper trainings offer to help customers. \n\nThis ApNote is merely an illustration of how to achieve simply good performance with little efforts. Ultimate performance will require more efforts, but starting (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}