{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"\u003Cabbr title=\"High Definition Multimedia Interface. Most widely used version is 1.4, but 2.0 starts becoming available (also as FPGA IP).\"\u003EHDMI\u003C\/abbr\u003E in (Rx)","author_name":"Bertrand Cuzeau, \nFrederic CALDAIROU","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/HDMI-in-Rx.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/HDMI-in-Rx.html'\u003E\u003Cabbr title=\"High Definition Multimedia Interface. Most widely used version is 1.4, but 2.0 starts becoming available (also as FPGA IP).\"\u003EHDMI\u003C\/abbr\u003E in (Rx)\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EALSE\u2019s HDMI Rx (sink) IP core decode the HDMI (1.4) serial data and generates a video streaming flow while supporting many display formats, up to Ultra-HD video (aka \u201c4K\u201d). Audio stream is supported. Note however that we do not offer the HDCP (contentss protection) decryption. \n\nWith a small footprint, affordable cost, and ease of use (does NOT require an embedded processor), this IP stands out from the competition and can be used in small and cheap FPGAs. \n\n Purpose \n\nThis core is designed (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}