{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"High Speed \u003Cabbr title=\"LVDS (Low Voltage Differential Signalling) is a standard that uses two signals to carry a value which is the (small) voltage difference between the two wires.\"\u003ELVDS\u003C\/abbr\u003E communication","author_name":"Bertrand Cuzeau","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/High-Speed-LVDS-communication.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/High-Speed-LVDS-communication.html'\u003EHigh Speed \u003Cabbr title=\"LVDS (Low Voltage Differential Signalling) is a standard that uses two signals to carry a value which is the (small) voltage difference between the two wires.\"\u003ELVDS\u003C\/abbr\u003E communication\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EPractically all FPGAs, even the low cost ones, offer the capability to create high-speed communication links based on LVDS signalling. If you think it\u2019s complex to use this capability, this article will prove you wrong. \n\n LVDS (Low Voltage Differential Signalling) is a standard that uses two signals (a \u201cpair\u201d) to carry a value which is the (small) voltage difference between the two wires. Typically, the voltage difference is small (0.4V eg) around a common mode voltage (1.2V eg). LVDS pairs (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}