{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"IPs","author_name":"Bertrand Cuzeau","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/IPs-125.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/IPs-125.html'\u003EIPs\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EAll our IPs are available on Intel FPGAs. \n\n -* AVB MILAN  Aurora 64B\/66B Aurora 8B\/10B Chip-Bridge (chip-to-chip link) 10GEDEK (10G Ethernet processor-less stack) GEDEK (1 Gigabit\/100M Ethernet processor-less stack) Remote update (through Ethernet RS232, RS485, SPI \u2026) JESD204B Tx+Rx NAND Flash Controller HyperRam Memory Controller PSRam Memory Controller LPDDR Memory Controller S\/PDIF HDMI in + HDMI out JPEG Video Encoder + Decoder NEW (2025) ! High-Speed JPEG Encoder De-bayer (up to 8k (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}