{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"JESD204","author_name":"Bertrand Cuzeau","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/JESD204.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/JESD204.html'\u003EJESD204\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EJESD204 is the Data Converter Serial Interface standard that was created through the JEDEC committee, with the participation of all the industrial providers of high-speed ADC and DACs (including Ti, Analog Devices etc). \n\nIf you want to use High Speed ADCs or DACs in your project, you need an FPGA with transceivers and a JESD204 IP ! \n\nAnd ALSE has JESD204 IPs available for many FPGA families and vendors. \n\nSee our Reference Design documentation below. \n\n Purpose \n\nThe first purpose of (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}