{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"JPEG Video Encoder","author_name":"Bertrand Cuzeau","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/JPEG-video-Encoder.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/JPEG-video-Encoder.html'\u003EJPEG Video Encoder\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EThis compact and extremely efficient core is capable of encoding in real-time video on-the-fly using standard and ubiquitous JPEG compression, even on low-cost FPGAs.  This IP does not require any processor nor any external memory. \n\n Purpose \n\nOur Baseline JPEG Encoder (Compression) core is capable of encoding video on-the-fly while producing standard JPEG compressed format. More efficient compression formats exist (we have also a 2D wavelet CODEC) and even inter-frame compression with (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}