{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"Legal mentions","author_name":"Bertrand Cuzeau","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/Mentions-legales.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/Mentions-legales.html'\u003ELegal mentions\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EPropri\u00e9taire du site \n\nBertrand Cuzeau. \n\nH\u00e9bergeur \n\nSiegler informatique, h\u00e9bergeur SPIP + SoyezCr\u00e9ateurs \n\nTerms of Use \n\n\u00a9 2009-2016 ALSE. All rights reserved. NOTICE OF DISCLAIMER about Free IPs and other information on the ALSE Web site. ALSE is providing design, code, or information \u201cas is.\u201d By providing the design, code, or information ALSE makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}