{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"PCA 9556 & 9557","author_name":"Jacques Pyrat","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/PCA-9556-9557.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/PCA-9556-9557.html'\u003EPCA 9556 & 9557\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EThese devices were I\u00b2C I\/O port extenders by Philips (now NXP). We have developed RTL models so you can add these functions to any FPGA. \n\nWe have developed an optimized IP that implements the same functionality as the PCA 9556 and 9557, with the ability to handle more ports and to fit in very small Programmable devices (one implementation fits in an 240 Macrocells CPLD). \n\nThe function performed by these devices is : Slave SMBus\/ I\u00b2C Ports I\/O Expander. \n\nThis function is not very complex, (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}