{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"Quad SPI Controller","author_name":"","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/Quad-SPI-Controller-98.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/Quad-SPI-Controller-98.html'\u003EQuad SPI Controller\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EFor an FPGA-based project, replacing bulky, pin-consuming, and complex Parallel Flash Memories by modern Quad-SPI Flash devices is very exciting in many respects.  It drastically reduces the FPGA pin count and thus enables smaller (and cheaper) packages. It also reduces the power consumption, minimizes the PCB area & complexity, reduces the BOM, while providing good transfer speed, etc\u2026 \n\nThe major issue against Quad SPI memories is that Parallel Flash Memories are usually much simpler (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}