{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"Intel Remote Update Application Note","author_name":"Bertrand Cuzeau","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/Remote-Update-Application-Note.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/Remote-Update-Application-Note.html'\u003EIntel Remote Update Application Note\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EWe have updated and re-published this Application Note created in 2010. It explains the principles and implementation of multi-boot in Altera now Intel FPGAs. \n\n The actual features available in the Intel FPGAs to allow the use of multiple configuration images in the external memory are actually far from trivial to use, and even 13 years later, the documentation remains a bit cryptic. \n\nWith practical examples in VHDL and SystemVerilog, and 6 complete projects including documented source (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}