{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"Remote Update for Lattice FPGAs","author_name":"Bertrand Cuzeau","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/Remote-Update-for-Lattice.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/Remote-Update-for-Lattice.html'\u003ERemote Update for Lattice FPGAs\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\u003Cp\u003EALSE’s \u003Cabbr title=\"Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc… Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.\"\u003EIP\u003C\/abbr\u003E for remote Update through Ethernet\u003C\/p\u003E\u003C\/blockquote\u003E\n"}