{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"SRAM Controller","author_name":"","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/SRAM-Memory-Controller.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/SRAM-Memory-Controller.html'\u003ESRAM Controller\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EA.L.S.E has developed a very compact and efficient Static RAM controller that can be easily integrated in any FPGA project. Main Technical Features High-Performance Controller supporting Burst Mode for Read\/Write transfers, to get optimized transfer speed and minimal switch fabric overhead. Asynchronous interface management with fastest Memory timings, depending FPGA and Memory speed grades, and Customer board Timing Constraints. 16\/32bits Slave Interface (Avalon-MM based) with Burst (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}