{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"Synchronous SRAM (SSRAM) Controller","author_name":"","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/Synchronous-SRAM-SSRAM-Controller.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/Synchronous-SRAM-SSRAM-Controller.html'\u003ESynchronous SRAM (SSRAM) Controller\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003ELow Latency is often very important in many fields such as cache-based products, broadcast, networking and communications applications, video streaming \/ video games, etc \u2026  Synchronous SRAM memories are very good candidates for such latency-sensitive applications, thanks to their (very) low latency (typically one clock cycle), high performance.  Interfacing such memories to an FPGA is easy using the optimized ALSE controller. Thanks to its very small FPGA footprint and low resource usage, (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}