{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"UVM Adopter","author_name":"Bertrand Cuzeau","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/UVM-Adopter-78.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/UVM-Adopter-78.html'\u003EUVM Adopter\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\u003Cp\u003EComplete 4-days \u003Cabbr title=\"Universal Verification Methodology. The convergence of many different vendor-specific Methodologies and the only one that is here to stay. It is based on SystemVerilog and especially the Classes (OOP) part of it. UVM is hard to learn and master.\"\u003EUVM\u003C\/abbr\u003E training. \u003Cbr class='manualbr' \/\u003E\/!\\ beware of pre-requisites though !\u003C\/p\u003E\u003C\/blockquote\u003E\n"}