{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"\u003Cabbr title=\"VHSIC Hardware Description Language. _ A consequence of the US DOD's VHSIC program, this language (normalized as IEEE 1076) was created to describe accurately the behavior of High Speed Integrated Circuits.\"\u003EVHDL\u003C\/abbr\u003E templates","author_name":"Bertrand Cuzeau","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/VHDL-Examples.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/VHDL-Examples.html'\u003E\u003Cabbr title=\"VHSIC Hardware Description Language. _ A consequence of the US DOD's VHSIC program, this language (normalized as IEEE 1076) was created to describe accurately the behavior of High Speed Integrated Circuits.\"\u003EVHDL\u003C\/abbr\u003E templates\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EIf you are looking for well-written code to analyze, or coding examples, please check also our Free IP section where you can find the source code of many IPs, which are reasonably simple to understand while implementing all the concepts needed for designing complex functions. \n\nWe have dedicated this page to Code Templates, so  beginners or more advanced designers can simply cut & paste from the snippets. There is enough code here to be used in 90% of VHDL code (both RTL and Simulation). (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}