{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"Z8030\/8530","author_name":"Jacques Pyrat","width":"480","height":"295","url":"http:\/\/www.alse-fr.com\/Z8030-8530-Zilog-SCC-Serial-Communication-Chip.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='http:\/\/www.alse-fr.com\/Z8030-8530-Zilog-SCC-Serial-Communication-Chip.html'\u003EZ8030\/8530\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EWe have developed a limited RTL model of the Zilog Z8030\/8530 - SCC Serial Communication Chip. We used it in combination with the model of the obsolete 6809 CPU to re-design an obsolete industrial board into an FPGA. \n\n Our model is currently not exhaustive: we have only modeled the UART (Asynchronous Serial communication functions) but not the Synchronous part. In other words, if your design uses the Synchronous mode, we don\u2019t have the right model off-the-shelf. \n\nIt\u2019s typically easy to (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}