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© Copyright 1997 ALSE VHDL Beginner's Corner VHDL Brain Teaser 2 !
(grade : easy / medium)
Trouvez les Erreurs !
(facile / moyen)
The VHDL code below exhibits some errors among the most common. Hints : If you cannot find what's wrong with this code, synthesize it and simulate it using this test bench.
Doing the Quiz :
- Understand
what the author tried to do.
- Explain
in no more than 10 lines of text what is wrong with this example.
- Fix
the source code but try to minimize the changes.
Note : You can simply cut and paste the text below to try it on your tools.
-- ----------------------------------------------------------------
-- This example does not work as expected by his author !
-- Find out why & fix it.
-- E-mail the solution atn :
-- Bert CUZEAU, info@alse-fr.com
-- © Copyright 1997 ALSE
------------------------------------------------------------------
-- Hints :
-- This design is supposed to catch the binary sequence "110" in DIN
-- The "Sync" output is intended to be combinatorial...
-- "Ovr" goes active after 16 ticks and no Synchro pattern detected.
--
-- Flaws :
-- * std_logic types would be better...
-- * many synthesis-related issues
-- * some simulation issues
-- * design is "late" catching the sequence
-- * Overflow detection doesn't work at all
-- * ...
-- ----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity SYNDET is
port (Clk : in bit;
Reset : in bit;
DIN : in bit;
Ovr : out bit;
Sync : out bit );
end SYNDET;
architecture behave of SYNDET is
signal Reg1 : bit;
signal Reg2 : bit;
signal Reg3 : bit;
signal Cnt : integer range 0 to 15;
begin
process (Clk)
begin
if (Reset = '1') then
Cnt <= 0;
Ovr <= '0';
elsif Clk='1' and Clk'event then
Reg1 <= Din;
Reg2 <= Reg1;
Reg3 <= Reg2;
Cnt <= (Cnt + 1) ; -- increment
if Cnt = 0 then -- test for overrun
Ovr <= '1';
end if;
if (Reg3 & Reg2 & Reg1 ) = bit_vector'("110") then
Sync <= '1';
Cnt <= 0;
else
Sync <= '0';
end if;
end if;
end process;
end behave;
-- ----------------------------------------------------------- |
