<?xml 
version="1.0" encoding="utf-8"?><?xml-stylesheet title="XSL formatting" type="text/xsl" href="http://www.alse-fr.com/spip.php?page=backend.xslt" ?>
<rss version="2.0" 
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:atom="http://www.w3.org/2005/Atom"
>

<channel xml:lang="en">
	<title>A.L.S.E the FPGA Experts</title>
	<link>https://www.alse-fr.com/</link>
	<description>A.L.S.E: Advanced Logic Synthesis for Electronics, offers a complete range of Services, IPs, Training courses and Boards to help you with the design of FPGA-based and EmbeddedSystems.</description>
	<language>en</language>
	<generator>SPIP - www.spip.net</generator>
	<atom:link href="http://www.alse-fr.com/spip.php?id_rubrique=1&amp;page=backend" rel="self" type="application/rss+xml" />

	<image>
		<title>A.L.S.E the FPGA Experts</title>
		<url>http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L144xH42/siteon0-d414d.png?1782755771</url>
		<link>https://www.alse-fr.com/</link>
		<height>42</height>
		<width>144</width>
	</image>



<item xml:lang="en">
		<title>Happy New Year</title>
		<link>http://www.alse-fr.com/Happy-New-Year.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/Happy-New-Year.html</guid>
		<dc:date>2025-01-08T08:26:27Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		



		<description>
&lt;p&gt;Best Wishes from ALSE The A.L.S.E Team in France wishes you all the best for 2026&#8230; &#8230; and will be at your side for your Digital Projects with our (FPGA &amp; ASIC) IPs, our Design Services, our Expertise and our Trainings !&lt;/p&gt;


-
&lt;a href="http://www.alse-fr.com/-NewsLetter-.html" rel="directory"&gt;NewsLetter&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_texte'&gt;&lt;h2 class=&#034;spip&#034;&gt;Best Wishes from ALSE&lt;/h2&gt;&lt;div class='spip_document_186 spip_document spip_documents spip_document_image spip_documents_left spip_document_left'&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH348/hny2026balse800-1bdfd.jpg?1782755772' width='500' height='348' alt='' /&gt;
&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;&lt;strong&gt;The A.L.S.E Team in France wishes you all the best for 2026&#8230;&lt;/strong&gt;&lt;br class='manualbr' /&gt;&#8230; and will be at your side for your Digital Projects&lt;br class='manualbr' /&gt;with our (&lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; &amp; &lt;abbr title=&#034;Application Specific Integrated Circuit. It is a Custom Design chip implementing usually many functions and designed by a customer. As opposed to Programmable devices or to ASSPs.&#034;&gt;ASIC&lt;/abbr&gt;) IPs, our Design Services,&lt;br class='manualbr' /&gt;our Expertise and our Trainings !&lt;/p&gt;&lt;/div&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>Formations en France</title>
		<link>http://www.alse-fr.com/Formations-en-France-121.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/Formations-en-France-121.html</guid>
		<dc:date>2022-12-07T12:31:46Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/logo/workbench1920.jpg" length="325052" type="image/jpeg" />


		<dc:subject>CycloShow</dc:subject>

		<description>&lt;p&gt;Attending an ALSE training is 95% guaranteed to be highly productive!&lt;/p&gt;

-
&lt;a href="http://www.alse-fr.com/-Fourre-tout-.html" rel="directory"&gt;Fourre-tout&lt;/a&gt;

/ 
&lt;a href="http://www.alse-fr.com/+-CycloShow-+.html" rel="tag"&gt;CycloShow&lt;/a&gt;

		</description>


 <content:encoded>&lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH80/workbench1920-09472.jpg?1782817786' class='spip_logo spip_logo_right' width='150' height='80' alt=&#034;&#034; /&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>Free IPs</title>
		<link>http://www.alse-fr.com/Free-IPs-120.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/Free-IPs-120.html</guid>
		<dc:date>2022-12-07T12:24:10Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/logo/entrepreneur-2275739_1920-2.jpg" length="214593" type="image/jpeg" />


		<dc:subject>CycloShow</dc:subject>

		<description>&lt;p&gt;For &lt;em class=&#034;spip&#034;&gt;Education purpose&lt;/em&gt;, we provide a few free &lt;strong&gt;simple&lt;/strong&gt; IPs for &lt;em class=&#034;spip&#034;&gt;personal&lt;/em&gt; use.&lt;br class='manualbr' /&gt;They are quite simple, but there is a lot to learn for beginners.&lt;/p&gt;

-
&lt;a href="http://www.alse-fr.com/-Fourre-tout-.html" rel="directory"&gt;Fourre-tout&lt;/a&gt;

/ 
&lt;a href="http://www.alse-fr.com/+-CycloShow-+.html" rel="tag"&gt;CycloShow&lt;/a&gt;

		</description>


 <content:encoded>&lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH84/entrepreneur-2275739_1920-2-caf51.jpg?1782817786' class='spip_logo spip_logo_right' width='150' height='84' alt=&#034;&#034; /&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>Design Services</title>
		<link>http://www.alse-fr.com/Design-Services.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/Design-Services.html</guid>
		<dc:date>2022-12-07T12:19:20Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/logo/hpapbb_hor_sm-2.jpg" length="430309" type="image/jpeg" />


		<dc:subject>CycloShow</dc:subject>

		<description>&lt;p&gt;No surprise: our core competence is Designing FPGAs (or ASICs), the more complex the better.&lt;/p&gt;

-
&lt;a href="http://www.alse-fr.com/-Fourre-tout-.html" rel="directory"&gt;Fourre-tout&lt;/a&gt;

/ 
&lt;a href="http://www.alse-fr.com/+-CycloShow-+.html" rel="tag"&gt;CycloShow&lt;/a&gt;

		</description>


 <content:encoded>&lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH67/hpapbb_hor_sm-2-00fef.jpg?1782817787' class='spip_logo spip_logo_right' width='150' height='67' alt=&#034;&#034; /&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>Ethernet Solutions</title>
		<link>http://www.alse-fr.com/Ethernet-Solutions.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/Ethernet-Solutions.html</guid>
		<dc:date>2022-12-07T12:01:30Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/logo/fiber-optic-2749588.jpg" length="621742" type="image/jpeg" />


		<dc:subject>CycloShow</dc:subject>

		<description>&lt;p&gt;Did you once evaluate the possibility of connecting an &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; to Ethernet and transferring data to/from a PC for example ? Did you reach the conclusion that it was very difficult and involved a lot of complex and bulky parts ?&lt;br class='manualbr' /&gt;Then it's time to re-consider !!!&lt;br class='manualbr' /&gt;Our &lt;abbr title=&#034;Gigabit Ethernet Data Exchange Kit. &#8220;Hardware Stack&#8221; Concept invented by ALSE, GEDEK is a processor-less autonomous block which implements the Ethernet protocols required to establish, maintain, and perform high performance data exchange over standard Ethernet.&#034;&gt;GEDEK&lt;/abbr&gt; IPs (100M, 1G, 2.5G, 5G or 10G) offer a new paradigm.&lt;/p&gt;

-
&lt;a href="http://www.alse-fr.com/-Fourre-tout-.html" rel="directory"&gt;Fourre-tout&lt;/a&gt;

/ 
&lt;a href="http://www.alse-fr.com/+-CycloShow-+.html" rel="tag"&gt;CycloShow&lt;/a&gt;

		</description>


 <content:encoded>&lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH100/fiber-optic-2749588-6ca37.jpg?1782817787' class='spip_logo spip_logo_right' width='150' height='100' alt=&#034;&#034; /&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>Intellectual Properties</title>
		<link>http://www.alse-fr.com/Intellectual-Properties.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/Intellectual-Properties.html</guid>
		<dc:date>2022-12-07T11:43:24Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/logo/lady-1721678_1920.jpg" length="718149" type="image/jpeg" />


		<dc:subject>CycloShow</dc:subject>

		<description>&lt;p&gt;ALSE Intellectual Property Blocks (&#8220;IPs&#8221;) are ready-to-use complex &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; functions that you can buy from A.L.S.E and integrate in your projects.&lt;/p&gt;

-
&lt;a href="http://www.alse-fr.com/-Fourre-tout-.html" rel="directory"&gt;Fourre-tout&lt;/a&gt;

/ 
&lt;a href="http://www.alse-fr.com/+-CycloShow-+.html" rel="tag"&gt;CycloShow&lt;/a&gt;

		</description>


 <content:encoded>&lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH79/lady-1721678_1920-b16e1.jpg?1782817787' class='spip_logo spip_logo_right' width='150' height='79' alt=&#034;&#034; /&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>+33(0)184163232</title>
		<link>http://www.alse-fr.com/33-1-84-16-32-32.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/33-1-84-16-32-32.html</guid>
		<dc:date>2016-08-31T14:15:28Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/logo/icon-157358.svg" length="740" type="image" />


		<dc:subject>Outils</dc:subject>

		<description>

-
&lt;a href="http://www.alse-fr.com/-Fourre-tout-.html" rel="directory"&gt;Fourre-tout&lt;/a&gt;

/ 
&lt;a href="http://www.alse-fr.com/+-Outils-+.html" rel="tag"&gt;Outils&lt;/a&gt;

		</description>


 <content:encoded>&lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L111xH150/icon-157358-5d95b.svg?1782817787' class='spip_logo spip_logo_right' width='111' height='150' alt=&#034;&#034; /&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>ALSE: Advanced Logic Synthesis for Electronics</title>
		<link>http://www.alse-fr.com/ALSE-Advanced-Logic-Synthesis-for-Electronics.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/ALSE-Advanced-Logic-Synthesis-for-Electronics.html</guid>
		<dc:date>2016-08-31T11:55:38Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		


		<dc:subject>EDITO</dc:subject>

		<description>
&lt;p&gt;Advanced Logic Synthesis for Electronics (&#8220;A.L.S.E&#8221;), offers a complete range of Design Services, Trainings, IPs, and Boards to help you with the design of FPGA-based applications or Embedded Systems. In general, we excel in Complex and High Performance Digital Systems. Discover ALSE through our Presentation Slide Show We have accumulated a lot of know-how and experience like: High Speed connectivity (100G &amp; beyond) with our Aurora 8B/10 and Aurora 64B/66B IPs. JESD204B (Tx + Rx) (&#8230;)&lt;/p&gt;


-
&lt;a href="http://www.alse-fr.com/-Fourre-tout-.html" rel="directory"&gt;Fourre-tout&lt;/a&gt;

/ 
&lt;a href="http://www.alse-fr.com/+-EDITO-+.html" rel="tag"&gt;EDITO&lt;/a&gt;

		</description>


 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Advanced Logic Synthesis for Electronics&lt;/em&gt; (&#8220;A.L.S.E&#8221;), offers a complete range of Design Services, Trainings, IPs, and Boards to help you with the design of &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt;-based applications or Embedded Systems.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;p&gt;In general, we excel in &lt;strong&gt;Complex and High Performance Digital Systems&lt;/strong&gt;.&lt;/p&gt;
&lt;p&gt;&lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/alse_short_gen_pres.pdf' class=&#034;spip_in&#034; title=&#034;Discover ALSE through our Presentation Slide Show &#8211; PDF (2.9 MiB)&#034; type='application/pdf'&gt;Discover ALSE through our Presentation Slide Show&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;We have accumulated a lot of know-how and experience like:&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; High Speed connectivity (100G &amp; beyond) with our &lt;strong&gt;Aurora 8B/10&lt;/strong&gt; and &lt;strong&gt;Aurora 64B/66B&lt;/strong&gt; IPs.&lt;/li&gt;&lt;li&gt; &lt;strong&gt;JESD204B&lt;/strong&gt; (Tx + Rx) IPs&lt;/li&gt;&lt;li&gt; NEW ! &lt;strong&gt;Chip-Bridge &lt;abbr title=&#034;Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc&#8230; Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.&#034;&gt;IP&lt;/abbr&gt;&lt;/strong&gt; for high speed Chip-To-Chip communication (remote AXI4)&lt;/li&gt;&lt;li&gt; &lt;strong&gt;10G Ethernet hardware stack&lt;/strong&gt; (no processor) : 10GEDEK&lt;/li&gt;&lt;li&gt; &lt;strong&gt;Gigabit (1G) Ethernet hardware stack&lt;/strong&gt; (no processor) : &lt;abbr title=&#034;Gigabit Ethernet Data Exchange Kit. &#8220;Hardware Stack&#8221; Concept invented by ALSE, GEDEK is a processor-less autonomous block which implements the Ethernet protocols required to establish, maintain, and perform high performance data exchange over standard Ethernet.&#034;&gt;GEDEK&lt;/abbr&gt;&lt;/li&gt;&lt;li&gt; &lt;em class=&#034;spip&#034;&gt;Video IPs&lt;/em&gt;. A lot ! iR acquisition and image processing. Video Compression/Decompression.&lt;/li&gt;&lt;li&gt; &lt;strong&gt;Memory Controller IPs&lt;/strong&gt; (Ram, Nand &amp; Nor Flash, HyperRam &#8230;)&lt;/li&gt;&lt;li&gt; Compact &lt;strong&gt;&lt;abbr title=&#034;High Definition Multimedia Interface. Most widely used version is 1.4, but 2.0 starts becoming available (also as FPGA IP).&#034;&gt;HDMI&lt;/abbr&gt;&lt;/strong&gt; in+out&lt;/li&gt;&lt;li&gt; &lt;strong&gt;Industrial Systems&lt;/strong&gt;: for data acquisition and processing, complex regulation, motor &amp; power control&#8230;&lt;/li&gt;&lt;li&gt; &lt;strong&gt;Industrial Networks&lt;/strong&gt; : Ultra-Low Latency Gigabit redundant Network with unequaled performance!&lt;/li&gt;&lt;li&gt; Stratix V GX &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; 8 channels Acquisition and Processing board, with 100G connectivity bandwidth.&lt;/li&gt;&lt;li&gt; &lt;strong&gt;Hardware Signal Processing&lt;/strong&gt;: ALSE has Implemented many FPGA-based digital signal processing (DSP) systems used in various fields ranging from electronic warfare systems to radio-astronomy to real-time acquisition.&lt;/li&gt;&lt;li&gt; Audio Systems: ALSE offers several audio IPs including a Digital Audio Processor (volume, tone control, ALC, loudness filter, InfraRed links&#8230;)&lt;/li&gt;&lt;li&gt; Avionics Systems: The internal know-how includes Arinc 429, Ethernet, secure systems, panel controls, PowerPC bridges, MILSTD 1553 bus&#8230;&lt;/li&gt;&lt;li&gt; Obsolescence or FPGA shortage mitigation : Redesign of entire boards or FPGA / vendor migration.&lt;/li&gt;&lt;li&gt; Services: &lt;abbr title=&#034;Hardware Description Language. _ Some HDLs are : Verilog, SystemVerilog, VHDL, SystemC. _ First-generation (now obsolete) HDLs : Abel, CUPL etc&#034;&gt;HDL&lt;/abbr&gt; Design review, &lt;abbr title=&#034;Application Specific Integrated Circuit. It is a Custom Design chip implementing usually many functions and designed by a customer. As opposed to Programmable devices or to ASSPs.&#034;&gt;ASIC&lt;/abbr&gt;/FPGA auditing, ASIC re-design, &lt;abbr title=&#034;VHSIC Hardware Description Language. _ A consequence of the US DOD's VHSIC program, this language (normalized as IEEE 1076) was created to describe accurately the behavior of High Speed Integrated Circuits.&#034;&gt;VHDL&lt;/abbr&gt; Certification&#8230;&lt;/li&gt;&lt;li&gt; Very High Temperature (200&#176;C) designs.&lt;/li&gt;&lt;li&gt; And indeed we have a very strong Training Activity, when we share our know-how with three portfolios.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Feel free to navigate in this website and discover our IPs, our services, and the various aspects of our daily activity.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_ps'&gt;&lt;p&gt;&lt;a href='http://www.alse-fr.com/Contact.html' class=&#034;spip_in&#034;&gt;Contact Us&lt;/a&gt; today to let us evaluate your requirements !&lt;/p&gt;&lt;/div&gt;
		</content:encoded>


		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/alse_short_gen_pres.pdf" length="3028051" type="application/pdf" />
		

	</item>
<item xml:lang="en">
		<title>Contact</title>
		<link>http://www.alse-fr.com/Contact.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/Contact.html</guid>
		<dc:date>2016-08-29T09:58:43Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/logo/letter-2794672_1920.jpg" length="152689" type="image/jpeg" />



		<description>&lt;p&gt;Ask for more information !&lt;/p&gt;

-
&lt;a href="http://www.alse-fr.com/-Fourre-tout-.html" rel="directory"&gt;Fourre-tout&lt;/a&gt;


		</description>


 <content:encoded>&lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH38/letter-2794672_1920-4ebb4.jpg?1782817787' class='spip_logo spip_logo_right' width='150' height='38' alt=&#034;&#034; /&gt;
		&lt;div class='rss_texte'&gt;&lt;div&gt;&lt;span class=&#034;base64php20953746186a524a425db8d3.36347121&#034; title=&#034;PD9waHAKaW5jbHVkZV9vbmNlKCIuLyIgLiBfRElSX1JBQ0lORSAuICJlY3JpcmUvYmFsaXNlL2Zvcm11bGFpcmVfLnBocCIpOwppZiAoJGxhbmdfc2VsZWN0ID0gImVuIikgJGxhbmdfc2VsZWN0ID0gbGFuZ19zZWxlY3QoJGxhbmdfc2VsZWN0KTsKaW5zZXJlcl9iYWxpc2VfZHluYW1pcXVlKGJhbGlzZV9GT1JNVUxBSVJFX19keW4oYXJndW1lbnRzX2JhbGlzZV9keW5fZGVwdWlzX21vZGVsZSgnRk9STVVMQUlSRV9GT1JNSURBQkxFJyksICdjb250YWN0JyksIGFycmF5KCcnLCAnJywgJycsICcnLCAnZW4nLCAnMScpKTsKaWYgKCRsYW5nX3NlbGVjdCkgbGFuZ19zZWxlY3QoKTsKPz4=&#034;&gt;&lt;/span&gt;&lt;/div&gt;&lt;/div&gt;
		
		</content:encoded>


		

	</item>



</channel>

</rss>