A.L.S.E the FPGA Experts

Asic to FPGA

2016-08-31T13:06:34Z

In some cases, you may have an old ASIC that becomes obsolete. You cannot afford to redesign a similar ASIC, yet you would like to avoid redesigning the complete system(s) that were using it.
Another case is wanting to include the functions performed by an obsolete ASIC into a new design. _A possible solution to this kind of problems is to use what you can recover from the original ASIC specification and design an FPGA based on this.

At ALSE, we've performed this kind of job quite a few times already.

In some cases, a lot of the original ASIC specification was lost (but we got high level description and a netlist) , at other times we had more complete functional description as well as expected values based on known stimuli.

These projects were not trivial but all successful in the end. In one case, a tweaking phase was necessary to painfully re-create the bugs and limitations of the original ASIC (!) since they contributed to create enormous databases of data that were exploited by sophisticated algorithms that took into account the ASIC exact behavior.

It is certainly not among our most typical projects, but we've been there, done that ;-)

System09

2016-08-31T13:06:32Z

System09, a 6809-based complete system-on-FPGA, does defeat 6809 Obsolescence !

What is System09 ?

Based on the excellent work of John Kent, in Australia, we have built in 2007 a fully synchronous (rising_edge) and cleaned up version of his 6809 processor.

We have also updated his System09 platform, which is now target-independent and verified by test benches and behavioral models, and has been tested on several Altera boards.

We have used this port in an industrial design.

The 6809 CPU fits in 2200 Logic Elements. As a consequence, a complete CPU board with many (obsolete) peripherals and even some memory can fit in a single and small FPGA.
This has applications beyond the nostalgic hobbyists !

How can I try it ?

You can download the bitstream of this System that runs on the old and cheap Terasic DE1 kit (Cyclone II) and you can test it very easily :

Program the DE1 with the DE1_System09_bitstream (.sof file).
Plug a PS/2 keyboard (QWERTY !)
Connect a screen to the VGA connector
Optionally : connect an RS232 cable on the serial port with a PC as terminal. Configure the terminal program (PuTTY or Hyperterminal eg) for 57600 bauds, N81, and no handshake.

That's it ! LEDr9 should “beat”, indicating that our design is loaded, and you should see the message “K_BUGS9S V1.0” followed by a prompt on the screen.

You can now enter 6809 Monitor commands using the Keyboard.
Note that the LEDs (LEDr0..8) monitor a part of the CPU address bus.

Try entering the following command (UPPERcase, spaces optional):
E FE00 FFFF.

The serial (RS232) port is operational and you can debug and load compiled code using a PC as a terminal (with the “L” command).
With the serial port, you don't even need the keyboard nor the VGA display.

Interested ?

If you need to convert an obsolete system that used a 6809 FPGA, ALSE can do this for you ! We will analyze your board, and see what other components beyond the CPU we can convert into an FPGA. Most of the time, we can convert the external SRams, the old E2Prom memories, some CPU peripherals (UART, Timers, PIOs etc).

Please contact us if you want to evaluate the opportunity to redesign an obsolete board.

You can also read our small article about Obsolescence.

Z8030/8530

2016-08-31T13:06:29Z

We have developed a limited RTL model of the Zilog Z8030/8530 - SCC Serial Communication Chip. We used it in combination with the model of the obsolete 6809 CPU to re-design an obsolete industrial board into an FPGA.

Our model is currently not exhaustive: we have only modeled the UART (Asynchronous Serial communication functions) but not the Synchronous part. In other words, if your design uses the Synchronous mode, we don't have the right model off-the-shelf.

It's typically easy to verify how the chip was used and make sure the RTL model will behave adequately.

The features of our IP are :

Two Independent, 0 to 2M Bits/Second, Full Duplex Channels, each with a Separate Baud Rate Generator (see below about ext osc emulation).
Asynchronous Mode with 5 to 8 Data Bits and 1, 1.5, or 2 Stop Bits per character,
Programmable Clock Factor, Break Detection and Generation, Parity, Overrun, and Framing Error Detection. Three interrupts are implemented.
Local Loopback and Auto Echo Modes
Fully synchronous implementation.
Emulation of the external oscillators using the internal clock source (removes the need for external oscillators).
Same register Set as the original part for software compatibility (in Asynchronous communication mode).
Deliverables include complete RTL source code (VHDL) with test benches and behavioral models.

If you are interested in this model, let us know, we could complete it if necessary for your project.

8254

2016-08-31T13:06:27Z

We have designed a synchronous but limited RTL model of the Intel 8254 Programmable Timer / Counter.

We have used this model in combination with the model of the 6809 CPU to re-design a complete obsolete industrial board into an FPGA.

Our 8254 model is currently not exhaustive: we have only modeled and tested the functions that were used in the design.

It's typically easy to verify how the 8254 was used, and make sure the RTL model will behave adequately.

If you are interested in this model, let us know, we could complete it if necessary for your project.

PCA 9556 & 9557

2016-08-31T13:06:25Z

These devices were I²C I/O port extenders by Philips (now NXP).
We have developed RTL models so you can add these functions to any FPGA.

We have developed an optimized IP that implements the same functionality as the PCA 9556 and 9557, with the ability to handle more ports and to fit in very small Programmable devices (one implementation fits in an 240 Macrocells CPLD).

The function performed by these devices is :

Slave SMBus/ I²C Ports I/O Expander.

This function is not very complex, so we deliver this IP in source code mode so the user can freely customize and re-use it.

When the original device had one port, our IP can have many 8-bits ports, this is a parameter in the IP core.

Moreover, the Voltage Levels and I/O standards will be those available on the FPGA. While being potentially an issue if 5V is required, it is usually and advantage when other levels are required.

A Demonstrator is available.