<?xml 
version="1.0" encoding="utf-8"?><?xml-stylesheet title="XSL formatting" type="text/xsl" href="http://www.alse-fr.com/spip.php?page=backend.xslt" ?>
<rss version="2.0" 
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:atom="http://www.w3.org/2005/Atom"
>

<channel xml:lang="en">
	<title>A.L.S.E the FPGA Experts</title>
	<link>https://www.alse-fr.com/</link>
	<description>A.L.S.E: Advanced Logic Synthesis for Electronics, offers a complete range of Services, IPs, Training courses and Boards to help you with the design of FPGA-based and EmbeddedSystems.</description>
	<language>en</language>
	<generator>SPIP - www.spip.net</generator>
	<atom:link href="http://www.alse-fr.com/spip.php?id_rubrique=31&amp;page=backend" rel="self" type="application/rss+xml" />

	<image>
		<title>A.L.S.E the FPGA Experts</title>
		<url>http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L144xH42/siteon0-d414d.png?1782755771</url>
		<link>https://www.alse-fr.com/</link>
		<height>42</height>
		<width>144</width>
	</image>



<item xml:lang="en">
		<title>La Scala !</title>
		<link>http://www.alse-fr.com/La-Scala.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/La-Scala.html</guid>
		<dc:date>2024-03-29T21:21:21Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		



		<description>&lt;p&gt;ALSE MILAN &lt;abbr title=&#034;Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc&#8230; Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.&#034;&gt;IP&lt;/abbr&gt; Carrier Board&lt;/p&gt;

-
&lt;a href="http://www.alse-fr.com/-Boards-.html" rel="directory"&gt;Boards&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;This Carrier Board, code-named &#8220;La Scala&#8221;, is designed to host the AVB64M Milan module and quickly prototype and develop Milan compatible professional Audio Equipment.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;div class='spip_document_203 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;48&#034; data-legende-lenx=&#034;x&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/jpg/lascalanomod.jpg' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/jpeg&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH253/lascalanomod-31318.jpg?1782818163' width='500' height='253' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-203 '&gt;&lt;strong&gt;La Scala Carrier Board (without AVB64M module)
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;&lt;h2 class=&#034;spip&#034;&gt;Purpose&lt;/h2&gt;
&lt;p&gt;The schematics of this board as well as the code of the on-board &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; are provided. &lt;br class='manualbr' /&gt;This allows the user to add his own functions and thus prototype products in a very short time.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Characteristics&lt;/h2&gt;&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; PCIe Gen1 x 1&lt;/li&gt;&lt;li&gt; Hosts the AVB64M Milan SODIMM Module&lt;/li&gt;&lt;li&gt; 2 x GBE RJ45 Ethernet connectors&lt;/li&gt;&lt;li&gt; Word Clock In + Out (SMB)&lt;/li&gt;&lt;li&gt; MADI in + MADI out (SMB)&lt;/li&gt;&lt;li&gt; AES3 inputs + outputs (HE10 2x5)&lt;/li&gt;&lt;li&gt; High End Stereo ADC with inputs (Jack 6.35mm)&lt;/li&gt;&lt;li&gt; High End stereo DAC with headphones Jack (6.35mm)&lt;/li&gt;&lt;li&gt; 2 x USB UARTs&lt;/li&gt;&lt;li&gt; AudioPrecision Debug Connectors&lt;/li&gt;&lt;li&gt; TDM interfaces (Tx + Rx HE10 1.27 2x10)&lt;/li&gt;&lt;li&gt; TPM secure module&lt;/li&gt;&lt;li&gt; 4 x LEDs, 2 x Push Buttons, 4 x DIPsw&lt;/li&gt;&lt;li&gt; External or PCIe Power Supply&lt;/li&gt;&lt;/ul&gt;&lt;/div&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>REFLEX CES Stratix 10 boards</title>
		<link>http://www.alse-fr.com/REFLEX-CES-Stratix-10-boards.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/REFLEX-CES-Stratix-10-boards.html</guid>
		<dc:date>2018-01-16T16:53:42Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		



		<description>
&lt;p&gt;This page highlights REFLEX CES' boards based on FPGA Stratix 10, the brand new FPGA by Intel -1- Sargon Instant-Development Kit Stratix 10 FPGA FMC+ PCIe board The Stratix 10 FPGA FMC+ Instant-Development Kit provides developers the best Out-Of-The box experience, combining the Best-In Class compact hardware platform with the most efficient intuitive software environment. Its unique install and GUI interface allows an immediate start, and its reference designs enable fast turn-around (&#8230;)&lt;/p&gt;


-
&lt;a href="http://www.alse-fr.com/-Boards-.html" rel="directory"&gt;Boards&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;This page highlights REFLEX CES' boards based on &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; Stratix 10, the brand new FPGA by Intel&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;p&gt;&lt;strong&gt;-1- Sargon Instant-Development Kit Stratix 10 &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; FMC+ PCIe board&lt;/strong&gt;&lt;/p&gt;
&lt;div class='spip_document_70 spip_document spip_documents spip_document_image spip_documents_center spip_document_center'&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/sargon_alse.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH234/sargon_alse-3cdb3.png?1782818163' width='500' height='234' alt='' /&gt;&lt;/a&gt;
&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;The Stratix 10 FPGA FMC+ Instant-Development Kit provides developers the best Out-Of-The box experience, combining the Best-In Class compact hardware platform with the most efficient intuitive software environment.&lt;/p&gt;
&lt;p&gt;Its unique install and GUI interface allows an immediate start, and its reference designs enable fast turn-around designs, shortening and securing developments.&lt;/p&gt;
&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Target markets&lt;/em&gt; : High Performance Computing and &lt;abbr title=&#034;Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc&#8230; Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.&#034;&gt;IP&lt;/abbr&gt; &amp; &lt;abbr title=&#034;Application Specific Integrated Circuit. It is a Custom Design chip implementing usually many functions and designed by a customer. As opposed to Programmable devices or to ASSPs.&#034;&gt;ASIC&lt;/abbr&gt; Prototyping&lt;/p&gt;
&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Benefits and features&lt;/em&gt; :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Intel Stratix 10 GX or SX 2800 KLEs&lt;/li&gt;&lt;li&gt; PCIe Gen3 x16, Gen4 x8 capable&lt;/li&gt;&lt;li&gt; Board Management Controller (BMC) for monitoring, EPCQ and clock programming, IPMI features&lt;/li&gt;&lt;li&gt; 1x FMC+ (VITA57.4) with 20 XCVR up to 28Gb/s&lt;/li&gt;&lt;li&gt; GPIO extension connector : 9 &lt;abbr title=&#034;LVDS (Low Voltage Differential Signalling) is a standard that uses two signals to carry a value which is the (small) voltage difference between the two wires.&#034;&gt;LVDS&lt;/abbr&gt; usable as 18 LVCMOS&lt;/li&gt;&lt;li&gt; XCVR extension connector : 10 XCVR, 8 LVDS, Clock In&amp;Out&lt;/li&gt;&lt;li&gt; 48 dedicated HPS IO connector (daughter board for SX)&lt;/li&gt;&lt;/ul&gt;&lt;div class='spip_document_71 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;42&#034; data-legende-lenx=&#034;x&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/sargon_bloc_diagram.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH217/sargon_bloc_diagram-5448d.png?1782818163' width='500' height='217' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-71 '&gt;&lt;strong&gt;Block diagram of Sargon Stratix 10 GX SX
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;&lt;strong&gt;-2- XpressGX/SX S10 FH200G&lt;/strong&gt;&lt;/p&gt;
&lt;div class='spip_document_74 spip_document spip_documents spip_document_image spip_documents_center spip_document_center'&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/xpressgxs10_alse.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH243/xpressgxs10_alse-90e02.png?1782818163' width='500' height='243' alt='' /&gt;&lt;/a&gt;
&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;The XpressGX/SX S10-FH200G board is a Full height profile PCIe Network Processing FPGA board, featuring 200G Ethernet.&lt;/p&gt;
&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Target markets&lt;/em&gt; : Data Center and Cloud Computing, Finance, High Performance Computing, Military &amp; Defense, Broadcast and Video&lt;/p&gt;
&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Benefits and features&lt;/em&gt; :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Full height PCIe board using Intel Stratix 10 GX or SX 2800 KLE&lt;/li&gt;&lt;li&gt; Designed for Acceleration and Low Latency Applications&lt;/li&gt;&lt;li&gt; PCIe Gen3 x16, Gen4 x8 capable&lt;/li&gt;&lt;li&gt; 3 independent banks on board DDR4&lt;/li&gt;&lt;li&gt; 2 independent banks on board QDR2+Xtrem&lt;/li&gt;&lt;li&gt; Dual QSFP28 optical cages, 10/25/40/100 GbE ports&lt;/li&gt;&lt;li&gt; 200G board to board capability (FireFly)&lt;/li&gt;&lt;li&gt; Board Management Controller (BMC) with IPMI features&lt;/li&gt;&lt;li&gt; IO and transceiver extension connectors&lt;/li&gt;&lt;/ul&gt;&lt;div class='spip_document_73 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;38&#034; data-legende-lenx=&#034;x&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/block_diagram_xpressgxs10v2.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH217/block_diagram_xpressgxs10v2-f50ac.png?1782818163' width='500' height='217' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-73 '&gt;&lt;strong&gt;block diagram of the XpressGX/SX S10
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;&lt;strong&gt;-3- COMXpressGX/SX Stratix 10&lt;/strong&gt;&lt;/p&gt;
&lt;div class='spip_document_75 spip_document spip_documents spip_document_image spip_documents_center spip_document_center'&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/comxpress_alse.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH380/comxpress_alse-bc9f5.png?1782818163' width='500' height='380' alt='' /&gt;&lt;/a&gt;
&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;The COMXpressGX/SX Stratix 10 is a COM Express Basic form factor Module, Type 7 standard&lt;/p&gt;
&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Target markets&lt;/em&gt; : High Performance Computing &amp; Analytics, Acceleration, Intelligent Vision, Video processing&lt;/p&gt;
&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Benefits and features&lt;/em&gt; :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; COM Express Basic form factor Module&lt;/li&gt;&lt;li&gt; Intel Stratix 10 Technology, GX and SX pin compatible&lt;/li&gt;&lt;li&gt; Designed for High Performance Computing and Acceleration&lt;/li&gt;&lt;li&gt; 32 PCI Express lanes, Type 7 standard&lt;/li&gt;&lt;li&gt; On board 56GB DDR4 + ECC&lt;/li&gt;&lt;li&gt; IO and Transceiver extended connector&lt;/li&gt;&lt;/ul&gt;&lt;div class='spip_document_72 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;32&#034; data-legende-lenx=&#034;x&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/block_diagram_comev2.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH305/block_diagram_comev2-fa9f6.png?1782818163' width='500' height='305' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-72 '&gt;&lt;strong&gt;block diagram of the COMXpress
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;&lt;/div&gt;
		&lt;div class="hyperlien"&gt;View online : &lt;a href="https://www.reflexces.com/products-solutions/development-kits/stratix-10" class="spip_out"&gt;Stratix 10 boards&lt;/a&gt;&lt;/div&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>REFLEX CES DevKits</title>
		<link>http://www.alse-fr.com/REFLEX-CES-DevKits.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/REFLEX-CES-DevKits.html</guid>
		<dc:date>2018-01-10T15:59:57Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/logo/arton111.jpg" length="189891" type="image/jpeg" />



		<description>
&lt;p&gt;REFLEX CES has developed many FPGA Development Kits and FPGA modules. This page highlights some of REFLEX CES' newest and most powerful kits, based on Arria 10 FPGA. -1- Achilles Instant-Development Kit Arria 10 SoC SoM The Arria 10 SoC SoM provides to developers the best Out-Of-The box experience combining the Best-In Class compact hardware platform and the most efficient intuitive software environment. Featuring an ARM dual-core Cortex-A9 MPCore and up to 660KLEs of advanced (&#8230;)&lt;/p&gt;


-
&lt;a href="http://www.alse-fr.com/-Boards-.html" rel="directory"&gt;Boards&lt;/a&gt;


		</description>


 <content:encoded>&lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH42/arton111-0dd57.jpg?1782818163' class='spip_logo spip_logo_right' width='150' height='42' alt=&#034;&#034; /&gt;
		&lt;div class='rss_chapo'&gt;&lt;p&gt;REFLEX CES has developed many &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; Development Kits and FPGA modules.
This page highlights some of REFLEX CES' newest and most powerful kits, based on Arria 10 FPGA.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;p&gt;&lt;strong&gt;-1- Achilles Instant-Development Kit Arria 10 SoC SoM &lt;/strong&gt;&lt;/p&gt;
&lt;div class='spip_document_67 spip_document spip_documents spip_document_image spip_documents_center spip_document_center'&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/achilles_alse.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH436/achilles_alse-6e66e.png?1782818163' width='500' height='436' alt='' /&gt;&lt;/a&gt;
&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;The Arria 10 SoC SoM provides to developers the best Out-Of-The box experience combining the Best-In Class compact hardware platform and the most efficient intuitive software environment. Featuring an ARM dual-core Cortex-A9 MPCore and up to 660KLEs of advanced low-power &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; logic elements, the Arria 10 SoC combines the flexibility and ease of programming of a CPU with the configurability and parallel processing power of an FPGA.&lt;/p&gt;
&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Target markets &lt;/em&gt; : Automotive, Video Broadcast, Machine and Intelligent Vision, Industrial, Military, Test &amp; Measurement and Medical.&lt;/p&gt;
&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Benefits and features&lt;/em&gt; :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Ultra compact form factor at only 86x95 mm (3.4x3.8 inches) is ideal for area constrained applications.&lt;/li&gt;&lt;li&gt; Careful board layout enables superior signal integrity, support for multi-Gigabit serial protocols, including PCIe Gen3 and 10G Ethernet.&lt;/li&gt;&lt;li&gt; Achilles Instant-DevKit is comprised of the Arria 10 SoC SoM plus a Starter board for quick prototyping and application testing.&lt;/li&gt;&lt;li&gt; Comprehensive reference designs available enable out-of-the-box experience, designs provided with source code.&lt;/li&gt;&lt;li&gt; Standard Linux Debian support, allows seamless porting of existing application software.&lt;/li&gt;&lt;/ul&gt;&lt;div class='spip_document_61 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;44&#034; data-legende-lenx=&#034;x&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/block_diagram_arria_10_soc_som.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH303/block_diagram_arria_10_soc_som-e1af4.png?1782818163' width='500' height='303' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-61 '&gt;&lt;strong&gt;Block diagram of Achilles Arria 10 SoC SOM
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;&lt;strong&gt;-2- Alaric Instant-Development Kit Arria 10 SoC FMC PCIe board&lt;/strong&gt;&lt;/p&gt;
&lt;div class='spip_document_69 spip_document spip_documents spip_document_image spip_documents_center spip_document_center'&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/alaric_alse.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH265/alaric_alse-61641.png?1782818164' width='500' height='265' alt='' /&gt;&lt;/a&gt;
&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;The Arria 10 SoC FMC Instant-Development Kit provides to developers the best Out-Of-The box experience combining the Best-In Class compact hardware platform and the most efficient intuitive software environment.&lt;/p&gt;
&lt;p&gt;Its unique install and GUI interface allows an immediate start, and its reference designs enable fast turn-around designs shortening and securing the developments.&lt;/p&gt;
&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Target markets:&lt;/em&gt; Video capture and processing, Industrial, Test &amp; Measurement and Medical.&lt;/p&gt;
&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Benefits and features &lt;/em&gt; :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Designed for high performance serial transceiver applications using series 10 SoC&lt;/li&gt;&lt;li&gt; Arria 10 SoC 660 KLEs in F34 package compliant 660 KLEs&lt;/li&gt;&lt;li&gt; PCIe device with 4 lanes at 8 Gb/s link rate (Gen3) and PCIe root with 4 lanes at 8 Gb/s link rate (Gen3)&lt;/li&gt;&lt;li&gt; Advanced memory interface with DDR3 on board Memory up to 4GB&lt;/li&gt;&lt;li&gt; Develop networking applications with 10/100/1000 Mbps Ethernet (GMII, RGMII and SGMII&#8203;)&lt;/li&gt;&lt;li&gt; Implement Video display applications with Display output port (up to 5.4Gbit/s)&lt;/li&gt;&lt;/ul&gt;&lt;div class='spip_document_59 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;38&#034; data-legende-lenx=&#034;x&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/alaric_board_diagram_v2.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH267/alaric_board_diagram_v2-4354a.png?1782818164' width='500' height='267' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-59 '&gt;&lt;strong&gt;Block diagram of Alaric Arria 10 SoC
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;&lt;br class='manualbr' /&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;-3- Attila Instant-Development Kit Arria 10 GX FMC PCIe board&lt;/strong&gt;&lt;/p&gt;
&lt;div class='spip_document_68 spip_document spip_documents spip_document_image spip_documents_center spip_document_center'&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/attila_alse.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH244/attila_alse-dcb79.png?1782818164' width='500' height='244' alt='' /&gt;&lt;/a&gt;
&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;The Arria 10 FPGA FMC Instant-Development Kit provides to developers the best Out-Of-The box experience combining the Best-In Class compact hardware platform and the most efficient intuitive software environment.&lt;/p&gt;
&lt;p&gt;Its unique install and GUI interface allows an immediate start, and its reference designs enable fast turn-around designs shortening and securing the developments.&lt;/p&gt;
&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Target markets&lt;/em&gt; : Test &amp; Measurement, Video capture and processing, High Performance Computing, Finance, Industrial and Medical&lt;/p&gt;
&lt;p&gt;&lt;em class=&#034;spip&#034;&gt;Benefits and features&lt;/em&gt; :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Designed for high performance serial transceiver applications&lt;/li&gt;&lt;li&gt; Arria 10 GX 1150 KLEs&lt;/li&gt;&lt;li&gt; PCIe with 8 lanes at 8 Gb/s link rate (Gen3)&lt;/li&gt;&lt;li&gt; Advanced memory interface with DDR4 SODIMM Memory up to 16 GB, support ECC and Non ECC&lt;/li&gt;&lt;li&gt; Enabling serial connectivity with QSFP+ with 4 XCVR links: 12.5 Gb/s per link&lt;/li&gt;&lt;li&gt; Develop networking applications with RJ45 copper connector 10/100/1000 Base-T Ethernet (Through RGMII &lt;abbr title=&#034;PHYsical Interface. Device in charge of handling (encoding and decoding) the lowest layer of the protocol (the physical signals). In case of Ethernet, the PHY chip is connected to the magnetics &amp;#38; RJ45 on one side, and offers a normalized data interface (MII, GMII, RGMII, SGMII etc).&#034;&gt;PHY&lt;/abbr&gt;&#8203;)&lt;/li&gt;&lt;li&gt; Implement Video display applications with Display output port Rev 1.2 (up to 5.4Gbit/s)&lt;/li&gt;&lt;li&gt; Expand I/O connector with 2 connectors in order to improve a front end of 32 high speed link&lt;/li&gt;&lt;li&gt; On board programmable PLL oscillator (Si5341), highly flexible and configurable clock generator/buffer&lt;/li&gt;&lt;/ul&gt;&lt;div class='spip_document_60 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;37&#034; data-legende-lenx=&#034;x&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/attila_board_diagram_v2.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH277/attila_board_diagram_v2-e453f.png?1782818164' width='500' height='277' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-60 '&gt;&lt;strong&gt;Block diagram of Attila Arria 10 GX
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;_&lt;/p&gt;&lt;/div&gt;
		&lt;div class="hyperlien"&gt;View online : &lt;a href="https://www.reflexces.com/products-solutions/development-kits" class="spip_out"&gt;REFLEX CES' development kits&lt;/a&gt;&lt;/div&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>IndEEx</title>
		<link>http://www.alse-fr.com/IndEEx.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/IndEEx.html</guid>
		<dc:date>2016-09-21T21:53:40Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		



		<description>
&lt;p&gt;IndEEx stands for INDustrial Ethernet EXtension. We developed this little inexpensive board in just a few days for the urgent need to add two Industrial Ethernet PHYs to a DE2-115 kit (which includes already two Gigabit PHYs). This extension is compatible with many inexpensive FPGA kits like DE0-nano, BeMicro-Max10, DE series etc. Extend low-cost FPGA kits with 2 x Industrial Ethernet ports ! Indeex is a small and simple add-on board that can extend low-cost FPGA kits with 2 x Industrial (&#8230;)&lt;/p&gt;


-
&lt;a href="http://www.alse-fr.com/-Boards-.html" rel="directory"&gt;Boards&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;IndEEx stands for &lt;strong&gt;IND&lt;/strong&gt;ustrial &lt;strong&gt;E&lt;/strong&gt;thernet &lt;strong&gt;EX&lt;/strong&gt;tension.&lt;br class='manualbr' /&gt;We developed this little inexpensive board in just a few days for the urgent need to add &lt;em class=&#034;spip&#034;&gt; two Industrial Ethernet PHYs&lt;/em&gt; to a DE2-115 kit (which includes already two Gigabit PHYs).&lt;br class='manualbr' /&gt;This extension is compatible with many inexpensive &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; kits like DE0-nano, BeMicro-Max10, DE series etc.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;div class='spip_document_32 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;45&#034; data-legende-lenx=&#034;x&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH406/indeex_web-205bc.jpg?1782818164' width='500' height='406' alt='' /&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-32 '&gt;&lt;strong&gt;Indeex: Industrial Ethernet Extension Board
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;&lt;h2 class=&#034;spip&#034;&gt;Extend low-cost &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; kits with 2 x Industrial Ethernet ports !&lt;/h2&gt;
&lt;p&gt;Indeex is a small and simple add-on board that can extend low-cost FPGA kits with &lt;strong&gt;2 x Industrial Ethernet ports&lt;/strong&gt; !&lt;/p&gt;
&lt;p&gt;The PHYs we used are TI 1588 Fast Ethernet PHYs, well supported by all Industrial Ethernet stacks.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Features&lt;/h2&gt;&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; &lt;/li&gt;&lt;/ul&gt;&lt;h2 class=&#034;spip&#034;&gt;Typical Application&lt;/h2&gt;
&lt;p&gt;Using this Extension board, you can turn the extremely inexpensive BeMicroMax10 kit into a PowerLink node !&lt;/p&gt;&lt;/div&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>Nina</title>
		<link>http://www.alse-fr.com/Nina.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/Nina.html</guid>
		<dc:date>2016-09-21T20:01:17Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		



		<description>
&lt;p&gt;Nina is a very simple add-on board that can be plugged into many cheap FPGA kits including the BeMicroMax10, the DE0-nano, the DE2 series etc. It provides a lot of extra peripherals and features including Ethernet and many more. Extend low-cost kits with Ethernet and many extra features! Nina is a small and simple add-on board that can extend low-cost kits (like the DE0-nano above) and add a lot of new peripherals and features, including Ethernet ! Features Ethernet (100M) Temperature (&#8230;)&lt;/p&gt;


-
&lt;a href="http://www.alse-fr.com/-Boards-.html" rel="directory"&gt;Boards&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;Nina is a very simple add-on board that can be plugged into many cheap &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; kits including the BeMicroMax10, the DE0-nano, the DE2 series etc. It provides a lot of extra peripherals and features including Ethernet and many more.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;div class='spip_document_30 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;29&#034; data-legende-lenx=&#034;&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/jpg/ninade0nano.jpg' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/jpeg&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH320/ninade0nano-6be94.jpg?1782818164' width='500' height='320' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-30 '&gt;&lt;strong&gt;Nina extending the DE0-nano
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;&lt;h2 class=&#034;spip&#034;&gt;Extend low-cost kits with Ethernet and many extra features!&lt;/h2&gt;
&lt;p&gt;Nina is a small and simple add-on board that can extend low-cost kits (like the DE0-nano above) and add a lot of new peripherals and features, including &lt;strong&gt;Ethernet &lt;/strong&gt; !&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Features&lt;/h2&gt;&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Ethernet (100M)&lt;/li&gt;&lt;li&gt; Temperature sensor&lt;/li&gt;&lt;li&gt; Position Encoder rotating button)&lt;/li&gt;&lt;li&gt; Accelerometer (3-axis)&lt;/li&gt;&lt;li&gt; UART over USB&lt;/li&gt;&lt;li&gt; Audio output&lt;/li&gt;&lt;li&gt; &lt;abbr title=&#034;LVDS (Low Voltage Differential Signalling) is a standard that uses two signals to carry a value which is the (small) voltage difference between the two wires.&#034;&gt;LVDS&lt;/abbr&gt; I/Os&lt;/li&gt;&lt;li&gt; RC-Servos connectors (2 axis)&lt;/li&gt;&lt;/ul&gt;&lt;h2 class=&#034;spip&#034;&gt;User's Guide&lt;/h2&gt;
&lt;p&gt;You can download here the &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/nina_ug_en.pdf' class=&#034;spip_in&#034; title=&#034;Nina User's Guide &#8211; PDF (635.2 KiB)&#034; type='application/pdf'&gt;Nina User's Guide&lt;/a&gt;.&lt;/p&gt;&lt;/div&gt;
		
		</content:encoded>


		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/nina_ug_en.pdf" length="650472" type="application/pdf" />
		

	</item>
<item xml:lang="en">
		<title>Hi-Res Analog</title>
		<link>http://www.alse-fr.com/Hi-Res-Analog.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/Hi-Res-Analog.html</guid>
		<dc:date>2016-09-17T06:53:21Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		



		<description>
&lt;p&gt;This Industrial Ethernet High-Resolution Data Acquisition Module is a ready-to-use instrument perfect for acquiring low frequency signals at very high resolution (24-bit) and driving Digital I/Os. Can be used as an Oscilloscope or as an Acquisition front-end driven by an easy-to-write custom software, or even as an AUTONOMOUS system! [TODO : insert image] Introduction This industrial Ethernet Data Acquisition Module is the best companion in any laboratory or for developing custom (&#8230;)&lt;/p&gt;


-
&lt;a href="http://www.alse-fr.com/-Boards-.html" rel="directory"&gt;Boards&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;This Industrial Ethernet High-Resolution Data Acquisition Module is a ready-to-use instrument perfect for acquiring low frequency signals at &lt;strong&gt;very&lt;/strong&gt; high resolution (24-bit) and driving Digital I/Os. Can be used as an Oscilloscope or as an Acquisition front-end driven by an easy-to-write custom software, or even as an AUTONOMOUS system!&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;p&gt;[TODO : insert image]&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Introduction&lt;/h2&gt;
&lt;p&gt;This industrial Ethernet Data Acquisition Module is the best companion in any laboratory or for developing custom applications demanding high resolution analog signal acquisition.
Digital I/O has been thrown in to provide a complete system that can even be rendered completely autonomous.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Sub-MicroVolts at your fingertips !&lt;/h2&gt;
&lt;p&gt;With 24-bit resolution and very low noise, this acquisition system can extract deeply hidden information in your signals.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Easy to Use&lt;/h2&gt;
&lt;p&gt;As compared to competitive systems using USB, the Ethernet connectivity provide immense advantages :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Reliable transfers with high bandwidth (up to 100 MBytes / sec)&lt;/li&gt;&lt;li&gt; No driver specific required&lt;/li&gt;&lt;li&gt; No painful installation&lt;/li&gt;&lt;li&gt; No common ground with the PC&lt;/li&gt;&lt;li&gt; The PC can be VERY far !&lt;/li&gt;&lt;li&gt; Cheap connectivity&lt;/li&gt;&lt;li&gt; a PC can drive several Acquisition modules.&lt;/li&gt;&lt;/ul&gt;&lt;h2 class=&#034;spip&#034;&gt;Use Examples&lt;/h2&gt;
&lt;p&gt;Complete Test bench for industrial measurements.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Unequalled Versatility&lt;/h2&gt;
&lt;p&gt;ALSE or our customers can even develop code for the internal &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; which is in charge of performing the ADC acquisition and the Ethernet communication.
The potential of this architecture is enormous ! You can develop autonomous real time hardware signal processing as well as Digital I/O control that runs in &lt;em class=&#034;spip&#034;&gt;real time&lt;/em&gt; without relying on a host processor !
An application example would be to perform complex (pun intended) measurements and calculation in real time (like active and reactive power measurements) and drive the digital outputs to perform safety functions.&lt;/p&gt;
&lt;p&gt;With these features, you'll find that there is no equivalent on the market.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;ALSE Framework&lt;/h2&gt;
&lt;p&gt;The system comes with a complete Reference Design using the SciLab open-source software. Our system is also indeed compatible with MATLAB and SIMULINK and potentially with any software (thanks to our documented UDP transport API).&lt;/p&gt;
&lt;p&gt;You can see the details in the [soon available Datasheet] or you can &lt;a href='http://www.alse-fr.com/Contact.html' class=&#034;spip_in&#034;&gt;contact us&lt;/a&gt;.&lt;/p&gt;&lt;/div&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>AVDB - Video Board (Obsolete)</title>
		<link>http://www.alse-fr.com/AVDB-Video-Board.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/AVDB-Video-Board.html</guid>
		<dc:date>2016-09-11T12:34:26Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		



		<description>
&lt;p&gt;To develop Video applications on FPGA or even to build video systems, AVDB was the perfect candidate, at an affordable cost. With embedded HDMI and DisplayPort connectivity, onboard DDR3, Gigabit Ethernet, SDI (with SFP+ module) and the largest Cyclone V FPGA, this board was an ideal platform for all kinds of projects, including 4K video ! Combined with the use of the Altera Video&lt;/p&gt;


-
&lt;a href="http://www.alse-fr.com/-Boards-.html" rel="directory"&gt;Boards&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;To develop Video applications on &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; or even to build video systems, &lt;abbr title=&#034;Advanced Video Development Board (Cyclone V board designed by ALSE for Video applications).&#034;&gt;AVDB&lt;/abbr&gt; was the perfect candidate, at an affordable cost. With embedded &lt;abbr title=&#034;High Definition Multimedia Interface. Most widely used version is 1.4, but 2.0 starts becoming available (also as FPGA IP).&#034;&gt;HDMI&lt;/abbr&gt; and &lt;abbr title=&#034;Digital and packet-based Display interface (royalty-free and developed by VESA) to connect a video source to a display device. _ Typically competing against HDMI.&#034;&gt;DisplayPort&lt;/abbr&gt; connectivity, onboard DDR3, Gigabit Ethernet, SDI (with SFP+ module) and the largest Cyclone V FPGA, this board was an ideal platform for all kinds of projects, including 4K video ! Combined with the use of the &lt;em class=&#034;spip&#034;&gt;Altera Video &lt;abbr title=&#034;Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc&#8230; Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.&#034;&gt;IP&lt;/abbr&gt; Suite&lt;/em&gt;, complete applications can be developed in just a few hours.&lt;/p&gt;
&lt;p&gt;Unfortunately, the production of this board is now stopped (some components -like the Enpirion regulators- being obsolete). Even our internal stock is now dry.&lt;/p&gt;
&lt;p&gt;If you can get a working board from some source, it's still an &lt;em class=&#034;spip&#034;&gt;excellent&lt;/em&gt; platform !&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;div class='spip_document_42 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;12&#034; data-legende-lenx=&#034;&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/jpg/avdb_description.jpg' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/jpeg&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH318/avdb_description-4a237.jpg?1782818164' width='500' height='318' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-42 '&gt;&lt;strong&gt;&lt;abbr title=&#034;Advanced Video Development Board (Cyclone V board designed by ALSE for Video applications).&#034;&gt;AVDB&lt;/abbr&gt; Board
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;This feature rich &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; board has been designed by ALSE to implement various challenging applications with a special focus on Video Acquisition, Processing, Displaying, and/or Streaming over Ethernet. For example, one or several &lt;abbr title=&#034;Advanced Video Development Board (Cyclone V board designed by ALSE for Video applications).&#034;&gt;AVDB&lt;/abbr&gt; boards can be plugged in a PC as a video I/O + video processing board for building COTS Servers.&lt;/p&gt;
&lt;p&gt;This industry-first board is propelled by an FPGA: the largest and fastest device from the low-cost 28 nm Altera Cyclone V GT family, which includes twelve 6.144 Gigabits transceivers, over 680 multipliers and 12+ megabits of internal memory.&lt;/p&gt;
&lt;p&gt;Combined with IPs available from Altera: &#8220;&lt;abbr title=&#034;Altera Video IP suite. A collection of IP blocks for Video Applications.&#034;&gt;VIP&lt;/abbr&gt;&#8221; (Video &lt;abbr title=&#034;Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc&#8230; Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.&#034;&gt;IP&lt;/abbr&gt; suite) or from ALSE, this board can address the most recent: protocols, processing and video formats (including Ultra HD &#8220;4K&#8221; video), with unprecedented performance.&lt;/p&gt;
&lt;p&gt;Video transformation, compression, decompression, format / rate changing or other complex algorithms can be implemented in the FPGA and run in real-time, outperforming the most powerful CPUs and associated software.&lt;/p&gt;
&lt;p&gt;This State-of-the Art High-End board is an excellent choice for Professional A/V Developers and Manufacturers. Moreover, its affordable price and its ability to fit in just any PC opens a realm of possibilities for creating and marketing very quickly new products and innovative solutions.&lt;/p&gt;
&lt;p&gt;To help you implementing video functions, you can check with our numerous high-performance Video IPs and also take advantage of the Altera Video IP Suite.
We have developed a lot of Demos and Reference Designs, a few of which are described in the &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/avdb_ref_designs.pdf' class=&#034;spip_in&#034; title=&#034;ADVB Reference Designs &#8211; PDF (1.1 MiB)&#034; type='application/pdf'&gt;ADVB Reference Designs&lt;/a&gt; document.&lt;/p&gt;
&lt;p&gt;You still can consult the &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/avdb_datasheet.pdf' class=&#034;spip_in&#034; title=&#034;AVDB Datasheet &#8211; PDF (1.5 MiB)&#034; type='application/pdf'&gt;AVDB Datasheet&lt;/a&gt;.&lt;/p&gt;
&lt;p&gt;The first batch was manufactured by Terasic.&lt;br class='manualbr' /&gt;The second iteration of AVDB (under the name of Clovis Video Kit) was manufactured in France and &lt;a href=&#034;https://www.reflexces.com/products/development-kits/cyclone-v-video-devkit/clovis&#034; class=&#034;spip_out&#034; rel=&#034;external&#034;&gt;sold worldwide by REFLEX CES&lt;/a&gt;.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_ps'&gt;&lt;p&gt;PS : As of 2024, if you buy &lt;abbr title=&#034;Advanced Video Development Board (Cyclone V board designed by ALSE for Video applications).&#034;&gt;AVDB&lt;/abbr&gt; (or the Clovis Kit) from a legitimate source, we can still provide some support !&lt;/p&gt;&lt;/div&gt;
		</content:encoded>


		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/avdb_ref_designs.pdf" length="1150264" type="application/pdf" />
		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/avdb_datasheet.pdf" length="1576515" type="application/pdf" />
		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/avdb_user_manual.pdf" length="2405339" type="application/pdf" />
		

	</item>
<item xml:lang="en">
		<title>HPAPB - Stratix V</title>
		<link>http://www.alse-fr.com/HPAPB-Stratix-V.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/HPAPB-Stratix-V.html</guid>
		<dc:date>2016-09-10T15:26:09Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		



		<description>&lt;p&gt;Stratix V Signal Acquisition and processing board&lt;/p&gt;

-
&lt;a href="http://www.alse-fr.com/-Boards-.html" rel="directory"&gt;Boards&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;This industrial board combines 8 x ADC channels (14 bits - 250 Ms/s - JESD204B) with the huge processing power of the largest Stratix V &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; (for signal processing applications).
&lt;abbr title=&#034;High Performance Acquisition and Processing Board : 8-channels Stratix V Signal Acquisition and Processing Board designed by ALSE.&#034;&gt;HPAPB&lt;/abbr&gt; has been designed to be used in a synchronized array built on a 40Gbits/s communication ring. An industrial rack, capable of hosting up to 10 boards (for a total of 80 ADC channels), is also available as an option.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;div class='spip_document_21 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;23&#034; data-legende-lenx=&#034;&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/jpg/hpapbb_hor_sm.jpg' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/jpeg&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH223/hpapbb_hor_sm-690fc.jpg?1782818164' width='500' height='223' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-21 '&gt;&lt;strong&gt;&lt;abbr title=&#034;High Performance Acquisition and Processing Board : 8-channels Stratix V Signal Acquisition and Processing Board designed by ALSE.&#034;&gt;HPAPB&lt;/abbr&gt; Stratix V board
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;&lt;h2 class=&#034;spip&#034;&gt;Introduction&lt;/h2&gt;
&lt;p&gt;This industrial Signal Acquisition and Processing board has been designed for :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Acquiring eight analog channels &lt;em class=&#034;spip&#034;&gt;synchronously&lt;/em&gt; (JESD204B) at very high speed (up to 250 Ms/s),&lt;/li&gt;&lt;li&gt; Implementing very dense and complex signal processing in the biggest and fastest Stratix V &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; from Altera (now Intel) connected to two very fast DDR3 memory modules.&lt;/li&gt;&lt;li&gt; Offering a huge communication bandwidth with neighbor HPAPBs, and with the external world (like GPU arrays etc)&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;&lt;strong&gt;Feature-rich&lt;/strong&gt;
With up to 32 Gigabytes of on-board DDR3 memory (2 slots), 2 x 10G SFP+ slots for 10G Ethernet (eg), and one Gigabit Ethernet port (for control and &#8220;low speed&#8221; transfers), &lt;abbr title=&#034;High Performance Acquisition and Processing Board : 8-channels Stratix V Signal Acquisition and Processing Board designed by ALSE.&#034;&gt;HPAPB&lt;/abbr&gt; offers unprecedented computing power and communication throughput. An on-board USB-Blaster II is included (with extra debug port feature for high data transfer speed).
The &lt;strong&gt;external 10 MHz Reference Clock&lt;/strong&gt; input associated with the &lt;strong&gt;PPS input&lt;/strong&gt; allow extremely accurate (ns) absolute time-stamping, perfect ADC synchronization, as well as multi-boards synchronization.
Moreover, it has been designed to communicate at very high speed (2 x 40 Gbits/s QSFP+) with neighbor cards (or other equipment), thus allowing cross-computation over an extremely large number of channels (for multiple synthetic aperture, beam-forming, sub-band analysis etc).&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Use Example&lt;/h2&gt;
&lt;p&gt;For example, HPAPB has been used successfully in a radio-astronomy application with 192 channels acquired and processed simultaneously. An industrial rack, capable of hosting up to 10 x boards, is available upon request (see picture below).
With close to 4,000 internal multipliers, the Stratix V GSD8 FPGA (largest device available) provides huge signal processing power (up to 1000 billions of multiplications per second !).
With 2 x 40G + 2 x 10G = over 100 Gigabits per second for communication throughput, HPAPB can move data between boards or with other processing systems at incredible rates, using standard low-cost cables up to several meters, or optical (fiber) adapters for longer connections.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;ALSE Framework and IPs&lt;/h2&gt;
&lt;p&gt;To help customers take the best advantage of the board's and FPGA's performance, A.L.S.E has developed specific IPs and a very powerful and versatile framework, from ADC data acquisition, to PLLs and synchronization control, to remote firmware update (with management of multiple configurations) through Ethernet, 10G Ethernet communication through hardware stack (10GEDEK), and many more.&lt;/p&gt;
&lt;p&gt;You can see the details in the &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/gif/freeip1.gif' class=&#034;spip_in&#034; title=&#034;HPAPB Datasheet &#8211; GIF (8.8 KiB)&#034; type='image/gif'&gt;HPAPB Datasheet&lt;/a&gt;.&lt;/p&gt;&lt;/div&gt;
		
		</content:encoded>


		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/hpapb_datasheet.pdf" length="1045006" type="application/pdf" />
		

	</item>
<item xml:lang="en">
		<title>ADM - Max 10</title>
		<link>http://www.alse-fr.com/ADM-Max-10-Module.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/ADM-Max-10-Module.html</guid>
		<dc:date>2016-09-09T22:24:05Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		



		<description>&lt;p&gt;Max10 plugin module compatible with Devboard's DBM3C modules.&lt;/p&gt;

-
&lt;a href="http://www.alse-fr.com/-Boards-.html" rel="directory"&gt;Boards&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;Powered by an Intel's Max10 &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt;, this affordable plugin module can replace (in many applications) the now old and hard to get DBM3C (Cyclone III) modules. &lt;br class='manualbr' /&gt;The Max10 is a recent FPGA family and is supported by the latest versions of Quartus Prime Standard. It also includes two embedded ADC converters.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;div class='spip_document_19 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;19&#034; data-legende-lenx=&#034;&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/jpg/adm.jpg' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/jpeg&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH440/adm-37050.jpg?1782818164' width='500' height='440' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-19 '&gt;&lt;strong&gt;ADM Max 10 Module
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;&lt;h2 class=&#034;spip&#034;&gt;Oct 2021 warning !&lt;/h2&gt;
&lt;p&gt;To date, we have exhausted our stock and have no possibility to procure the &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; (and some other parts) within a reasonable delay. If you are interested by this board, please contact us ASAP. We may redesign this board to use different and more available components.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Replacing old modules&lt;/h2&gt;
&lt;p&gt;ADM is compatible with DBM3C modules : it can be plugged in the same baseboards. We developed this simple module for our own needs including a Gigabit Ethernet concentrator driving multiple remote controllers through optical fibers.
This module can be helpful for similar applications that were developed for older DBM modules, thus we made it available off the shelf. The Max10 FPGA also offers 2 x ADC (Analog to Digital Converters) not available on the original modules.
The ADM board is compatible with a larger Max10 (50k LEs), contact ALSE for stock availability.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Caveat Emptor&lt;/h2&gt;
&lt;p&gt;Note however that this module does not implement the external memory nor the external Flash as compared to the original DBM modules, so it is not functionally equivalent and may not be suitable for any replacement. An analysis of the features used by the DBM design is necessary to verify whether ADM can be used as a replacement.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Block Diagram&lt;/h2&gt;&lt;div class='spip_document_33 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;19&#034; data-legende-lenx=&#034;&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/png/adm_blockdiagram.png' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/png&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH280/adm_blockdiagram-e5d52.png?1782818164' width='500' height='280' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-33 '&gt;&lt;strong&gt;ADM Block Diagram
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;&lt;h2 class=&#034;spip&#034;&gt;Gigabit Ethernet Connectivity made Easy&lt;/h2&gt;
&lt;p&gt;ADM is well suited for (Gigabit) Ethernet connectivity applications, especially when using ALSE's &lt;abbr title=&#034;Gigabit Ethernet Data Exchange Kit. &#8220;Hardware Stack&#8221; Concept invented by ALSE, GEDEK is a processor-less autonomous block which implements the Ethernet protocols required to establish, maintain, and perform high performance data exchange over standard Ethernet.&#034;&gt;GEDEK&lt;/abbr&gt; &lt;abbr title=&#034;Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc&#8230; Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.&#034;&gt;IP&lt;/abbr&gt;.&lt;/p&gt;
&lt;p&gt;You can download here the &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/adm_datasheet.pdf' class=&#034;spip_in&#034; title=&#034;ADM Datasheet here &#8211; PDF (322.5 KiB)&#034; type='application/pdf'&gt;ADM Datasheet here&lt;/a&gt;.&lt;/p&gt;&lt;/div&gt;
		
		</content:encoded>


		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/adm_datasheet.pdf" length="330289" type="application/pdf" />
		

	</item>
<item xml:lang="en">
		<title>HPPB - Stratix IV (Obsolete)</title>
		<link>http://www.alse-fr.com/HPPB.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/HPPB.html</guid>
		<dc:date>2016-09-09T17:36:02Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		



		<description>&lt;p&gt;High Performance Altera Stratix IV Acquisition &amp; Processing Board.&lt;br class='manualbr' /&gt;This board is &lt;strong&gt;obsolete&lt;/strong&gt;. It has been replaced in 2015 by &lt;abbr title=&#034;High Performance Acquisition and Processing Board : 8-channels Stratix V Signal Acquisition and Processing Board designed by ALSE.&#034;&gt;HPAPB&lt;/abbr&gt; (Stratix V).&lt;/p&gt;

-
&lt;a href="http://www.alse-fr.com/-Boards-.html" rel="directory"&gt;Boards&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;This High Performance Acquisition &amp; Processing &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; Board, based on Altera Stratix IV FPGA, exists in two versions.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;div class='spip_document_16 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;12&#034; data-legende-lenx=&#034;&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH229/hpbbvaweb-5338c.jpg?1782818164' width='500' height='229' alt='' /&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-16 '&gt;&lt;strong&gt;HPBB Board
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;We designed this very complex board above to deliver the highest performance on the market (at this time). This board existed in two versions : one to be used with an FMC108 8 channels ADC daughter board, and one to be used with an FMC150 ADC + DAC daughter board.
Note that, after this board, we developed a more powerful Stratix V board (see &lt;abbr title=&#034;High Performance Acquisition and Processing Board : 8-channels Stratix V Signal Acquisition and Processing Board designed by ALSE.&#034;&gt;HPAPB&lt;/abbr&gt;).&lt;/p&gt;
&lt;p&gt;With 16 &lt;abbr title=&#034;Printed Circuit Board. A key and potentially extremely complex piece in any project.&#034;&gt;PCB&lt;/abbr&gt; routing layers, 3 x DDR3 memory interfaces, support for 2 x QSFP and 2 x SFP+ modules, 4 x SATA II connectors, ready-to-use framework with ultra-high performance Gigabit Ethernet links and a High Pin Count FMC-VITA extension connector, we deliver a unique platform with unmatched performance. Harnessing this power is easy thanks to our framework : customers can build complete applications in just a few hours.&lt;/p&gt;
&lt;p&gt;This board can host a 4DSP-FMC108 extension daughter card offering 8 x ADC channels x 14 bits x 250 Ms/s. We have tested and qualified the team HPBB+FMC108 for analog acquisition and the results are excellent thus proving the quality of the design and layout. Likewise, our live signal integrity measurements of the DDR3 interfaces are extremely good with the largest capture windows, allowing the use of these memories at the maximum frequency with an excellent safety margin.&lt;/p&gt;
&lt;p&gt;The complete FMC108 interface and driver (internal PLL control synchronized ADC interface) are available and ready to use.&lt;/p&gt;
&lt;p&gt;The FMC150 version provides a solution when both Signal Acquisition AND generation is desired.&lt;/p&gt;
&lt;p&gt;With the very high processing power of the Stratix IV GX, the HPBB series allowed for challenging acquisition and real-time processing applications.&lt;/p&gt;
&lt;p&gt;You can still download here the &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/hpbbv2_product_brief.pdf' class=&#034;spip_in&#034; title=&#034;HPBB Product Brief &#8211; PDF (277.1 KiB)&#034; type='application/pdf'&gt;HPBB Product Brief&lt;/a&gt;.&lt;/p&gt;&lt;/div&gt;
		
		</content:encoded>


		
		<enclosure url="http://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/hpbbv2_product_brief.pdf" length="283795" type="application/pdf" />
		

	</item>



</channel>

</rss>