A.L.S.E the FPGA Experts

High-Speed JPEG Video Encoder

2024-12-31T10:46:55Z

This is a “dual-core” version of our standard JPEG encoder.
It is still compact enough and efficient to fit in a very small low cost FPGA while allowing real time compression at higher resolutions than Full-HD at 60fps.
It has an option to generate a video stream optimized for GPU decoding ! This is a unique feature on the market, now tested and used on high-end commercial products.
This IP does not require any processor nor any external memory.

Purpose

This “Dual-Core” High-Speed Baseline JPEG Encoder (Compression) core is capable of encoding video on-the-fly while producing standard JPEG compressed format. Its “Dual-core” architecture doubles the compression speed as compared to our standard baseline JPEG Encoder. The use of JPEG compression allows using very small FPGAs without external memory, leading to very economical systems, and our dual-core architecture allows high resolution and frame rates compression on low cost FPGAs.

Architecture

ALSE HighSpeed (dual-core) JPEG Encoder

Easy to use

Our core is compact and implements standard interfaces, so it can be used easily either as a standalone block, or as part of a Platform Designer system (or equivalent).

Again : it does not require any embedded processor nor external memory. It is small and efficient enough to fit easily in low cost and small FPGAs, like in the Altera Cyclone and Agilex 3 families, or the Lattice FPGA families (eg ECP3, ECP5, Certus-NX, CertusPro-NX, Crosslink-NX, Mach-XO5 etc) or the Microchip FPGAs (Igloo 2 or Polarfire).

It fits (indeed) very well in higher-end families (Altera Agilex 5 or Agilex 7, Lattice Avant-X and Avant-G etc), thus offering the capability to support high resolutions and frame rates. Our simulation environment can be helpful to develop and the application that includes the JPEG encoder.

Main Technical characteristics

Speed and Area-Optimized encoder (dual-core) engine
Suitable for both still image and real-time video compression.
8 bits (byte) Streaming output interface with Backpressure. Easy to connect to the ALSE Ethernet communication engine for example. Output format is 8x8 YUV Blocks (4:2:2).
Option to generate a video stream optimized for multi-thread GPU decoding !
Supports any image resolution up to 64k x 64k.
Standard Huffman table.
Dynamically configurable Quantization tables (up to 8 tables) for multiple levels of compression and quality.
Dynamic choice of compression level (can be adjusted automatically).
Can be easily integrated in a complete video system using the ALSE “Block to Raster” module, a Memory Frame Buffer and a Video Output Controller (RGB outputs for VGA, LCD; YUV BT656, etc … )
Versatile. This IP can be used in all FPGA devices (internal memory blocks must indeed be available).
Compact.
Fast : excellent Fmax on all FPGA families.
First-class Technical Support (E-mail and Telephone, extended CET hours).
Customization to specific needs is possible.
Verification Environment with advanced test benches.

Best in class

Some ALSE IPs also exist in the competition, JPEG Codec is in this case. However, our IP offers unique characteristics and advantages.

More compact.
More efficient than the competition.
Faster (better Fmax).
Dual-engine version.
Optimized for multi-thread decoding (GPU) -encoder option-.

Demos available

We have many demos created for many FPGA boards.

JPEG Video Decoder

2016-09-20T20:47:05Z

This compact and extremely efficient core is capable of decoding in real-time video on-the-fly using standard and ubiquitous JPEG compression, even on low-cost FPGAs.
This IP does not require any processor nor any external memory.

Purpose

Our Baseline JPEG Decoder (Decompression) core is capable of decoding JPEG-compressed video on-the-fly and produce raw video stream.

For streaming decoding of High Resolution (like Full-HD) on low cost FPGAs, two decoders in parallel may be used.

Easy to use

Our core is compact and implements standard interfaces, so it can be used easily either as a standalone block, or as part of a Qsys system. Again : it does not require any embedded processor. It is small and efficient enough to fit easily in low cost and small FPGAs (like Cyclone V). With two instances working in parallel, it is possible to decode Full-HD in real time.

The core can be used as a stand-alone block or with Qsys, with or without the Altera Video IP suite (“VIP”).

Our simulation environment can be helpful to develop and the application that includes the JPEG decoder.

This core has been used (with the corresponding JPEG Encoder) in a very successful consumer product.

This IP core is also used in many Demos and Reference Designs that are available with ALSE's AVDB Video board. In many cases, purchasing an AVDB board to develop or to prototype the application will make a lot of sense.

Main Technical characteristics

Speed and Area-Optimized engine suitable for both still image and real-time video compression.
8 bits (byte) Streaming input interface with Backpressure. Easy to connect to the ALSE Ethernet communication engine for example.
Standard Huffman table.
Dynamic Quantization tables extracted automatically from the input stream
Versatile. This IP can be used in most FPGA families (internal memory blocks must be available).
Compact. On an Altera Device, the area is typically less than 3500 Logic Elements, 5 memory blocks and 9 DSP18-bits (multipliers) are used.
Fast : on an old Altera EP3C25F256C6 Cyclone III Device, the Decoder can run at more than 180 MHz.
First-class Technical Support (E-mail and Telephone, extended CET hours).
Customization to specific needs available.

Best in class

Some ALSE IPs also exist in the competition, JPEG Decoder is in this case. However, our IP offers unique characteristics and advantages.

More compact.
More efficient than the competition.
Faster.

Demos available

We have many demos created for several FPGA boards, including our AVDB Video Development Board.

Information available

A datasheet is available, but do not hesitate to contact us if you want more details.

ALSE demo : Streaming Full-HD on PowerLines
HDMI -> JPEG Encoder -> GEDEK -> Ethernet -> GEDEK -> JPEG Decoder -> HDMI

And MANY more !

2016-09-20T20:34:16Z

We probably already have the video processing block you need ;-)

We have developed a lot of other video processing blocks :

Frame Buffer

Uses External Memory (typically DDRx) to buffer video frames and allow sender and receiver to operate at very slightly to very different rates. A comparable IP exists in the VIP, but we can trim our IP to specific needs.

RGB ↔ 4:2:2 Color Space Converters

ALSE has developed several color space converters to switch from RGB to YCbCr 4:4:4 or 4:2:2. These functions receive and transmit data through Standard Streaming Interfaces.
Several versions are available to handle different video formats from HD (720p and 1080p) to UHD (2160p aka “4K”) by using 4 Pixels In Parallel.

Demosaic-ing / CFA interpolators / Debayer

This IP interpolates RGB values for each pixel for sensors who only deliver one color per pixel (like through a Bayer filter).

Without much surprise, we have three different IPs for this function :

the simplest and very small (nearest neighbor)
the 3x3 matrix 2D interpolator
the highest quality using sophisticated algorithms for the interpolation. The High-Quality filter has been tested by customers as providing the best quality (they compared with several other IPs).

Video Data Path Adapters (2 PIP ↔ 4 PIP in RGB/4:4:4 or 4:2:2 mode)

These adapters allow to extend or reduce the video data-path of video blocks compatible with the Intel Avalon ST-Video protocol. It offers a way to switch from 2 to 4 (or 4 to 2) Pixels In Parallel (a larger datapath indeed means the ability to use a slower clock).

Scalers (1080p ↔ 2160p / 1080p ↔ 720p)

These video scalers can be used in video designs to rescale the image :

720p → 1080p
1080p → 720p They are using simple interpolation to reduce the logic resources required and use Avalon Video-ST Interfaces.

Test Pattern Generator

The Test Pattern Generator designed by ALSE is useful for system tuning or to test an output interface from a video pipeline. The output test frame is divided in two sections : the upper section is composed of color stripes which are shifted every second and the lower section is composed of fixed gray scales stripes. Interface used : Avalon-ST Video. Video color modes supported : RGB / 4:4:4 / 4:2:2 / 4:2:0 with 8,10,12, 14 or 16 bits per color Supports : 1 PIP/2 PIP/4 PIP (PIP : Pixels In Parallel)

Audio Generator

This audio generator can be used to test the audio data-path in a system.
It generates a sine wave using an “A” frequency (440 Hz) and outputs data on a streaming interface. The audio sampling rate is configurable at compilation.

And still more !

Whatever you're looking for in the video processing space, you can always contact us to see if we can help you.

EDID manager

2016-09-20T20:08:43Z

This IP is actually two IPs in one and can manage the EDID Tables used in HDMI to let the sink (rx) disclose the video (and audio) formats that it supports.

The two IP blocks are :

EDID Table Provider

This function includes an EDID Table provided by the user and an I2C Slave in order to manage the Display Data channel of a HDMI Sink device. It allows to specify the video and audio formats expected by the Sink.

EDID Table Parser

This small function can be used in conjunction with the HDMI Source IP Core to manage the Display data Channel of a HDMI Source Interface. This core includes an I2C Master and a custom logic to analyze video formats available in the EDID Table of a display monitor and returns the video format to use for a given Pixel clock frequency.

Compact - no Processor needed

Neither blocks require a processor to work.

HDMI in (Rx)

2016-09-20T19:37:40Z

ALSE's HDMI Rx (sink) IP core decode the HDMI (1.4) serial data and generates a video streaming flow while supporting many display formats, up to Ultra-HD video (aka “4K”).
Audio stream is supported.
Note however that we do not offer the https://en.wikipedia.org/wiki/High-bandwidth_Digital_Content_Protection].">HDCP (contentss protection) decryption.

With a small footprint, affordable cost, and ease of use (does NOT require an embedded processor), this IP stands out from the competition and can be used in small and cheap FPGAs.

Purpose

This core is designed to add an HDMI input to an FPGA, only requiring a connector (and optionally an ESD protection circuit to protect the FPGA.

Indeed, it requires the use of 4 x SERDESes in the FPGA.

Note that we do not implement https://en.wikipedia.org/wiki/High-bandwidth_Digital_Content_Protection].">HDCP (contents protection by encryption).

Easy to use

Our core is compact and implements standard interfaces, so it can be used easily either as a standalone block, or as part of a Qsys system. It does not require an embedded processor.

This core is small and efficient enough to fit easily in a low cost and small FPGA, like in the Intel Cyclone V family.

Main Technical characteristics

Video formats supported :
- HD-ready (720p)
- Full-HD (1080p)
- UHD (2160p), 24 bits per pixel (16M colors)

Decodes main auxiliary packets such as Auxiliary Video Information, Audio InfoFrame, General Control Packet, HDMI Vendor-Specific InfoFrame
Receives video and audio (L-PCM)
Transmits main auxiliary packets such as Auxiliary Video Information, Audio InfoFrame, General Control Packet, HDMI Vendor-Specific InfoFrame
Output interface :
- Avalon ST-Video
- Avalon ST for audio stream (user packet)
- Parallel Interface (Vsync, Hsync, Data Enable)
  this allows using this core easily with Qsys and the Altera Video IP suite (“VIP”).
Implements an user-editable EDID table.

Other settings and adapting the IP core to specific demands can be available upon request.

Demos are available

on Arria 10 (Attila kit from Reflex with FMC HDMI Daughter Card from Bitec) : Full-HD and UHD Formats.

This IP is one of the few that cannot be simply demonstrated on our AVDB Video Dev Kit (because we have a raw DisplayPort input, and the HDMI input uses an Aanlog Device Decoder chip).

If you have an Arria10 kit and a Bitec HDMI2.0 adpater, we can send you a demo bitstream !

HDMI out (TX)

2016-09-17T09:49:19Z

ALSE's HDMI Tx (source) IP core takes a video streaming flow as an input and generates video output signals compliant to the HDMI 1.4 standard while supporting many display formats, up to Ultra-HD video (aka “4K”).

With a small footprint, affordable cost, and ease of use (does NOT require an embedded processor), this IP stands out from the competition and can be used in small and cheap FPGAs.

Purpose

This core is designed to add an HDMI output to an FPGA, only requiring a connector (and optionally a re-driver to isolate the FPGA and enhance the transmission strength).

It requires the use of 4 x SERDESes in the FPGA.

Note that we do not implement https://en.wikipedia.org/wiki/High-bandwidth_Digital_Content_Protection].">HDCP (contents protection by encryption).

Easy to use

Our core is compact and implements standard interfaces, so it can be used easily either as a standalone block, or as part of a Qsys system. It does not require an embedded processor.

This core is small and efficient enough to fit easily in a low cost and small FPGA, like in the Intel Cyclone V family.

This IP core is used in most Reference Designs that are available with ALSE's AVDB Video board. In many cases, purchasing an AVDB board to develop or to prototype the application will make a lot of sense.

Main Technical characteristics

Video formats supported :
- HD-ready (720p)
- Full-HD (1080p)
- UHD (2160p), 24 bits per pixel (16M colors)

The core handles 1 pixel per clock cycle for 720p and 1080p formats, and 4 pixels per clock cycle for UHD.
Supports different color spaces : RGB / 4:4:4 / 4:2:2 / 4:2:0 for 2160p60 or 2160p50
Includes video timings for following :
- 720p50
- 720p60
- 1080p24
- 1080p25
- 1080p30
- 1080p50
- 1080p60
- 2160p24
- 2160p25
- 2160p30
- 2160p50* / 2160p60* (* : in 4:2:0 only)
Transmits video and audio (L-PCM)
Transmits main auxiliary packets such as Auxiliary Video Information, Audio InfoFrame, General Control Packet, HDMI Vendor-Specific InfoFrame
Input interface : Avalon Video-ST (also for audio stream)
this allows using this core easily with Qsys and the Altera Video IP suite (“VIP”).
Implements an user-editable EDID table.

Other settings and adapting the IP core to specific demands can be available upon request.

Demos are available

Among which:

on Cyclone V (AVDB) : HD-Ready-720p / Full-HD-1080p / UHD-2160p
on Arria 10 (Attila kit from Reflex with FMC HDMI Daughter Card from Bitec) : Full-HD and UHD Formats.

JPEG Video Encoder

2016-09-17T09:28:50Z

This compact and extremely efficient core is capable of encoding in real-time video on-the-fly using standard and ubiquitous JPEG compression, even on low-cost FPGAs.
This IP does not require any processor nor any external memory.

Purpose

Our Baseline JPEG Encoder (Compression) core is capable of encoding video on-the-fly while producing standard JPEG compressed format. More efficient compression formats exist (we have also a 2D wavelet CODEC) and even inter-frame compression with motion estimation, but these techniques are much more bulky. JPEG allows using very small FPGAs without using external memory, leading to very economical systems.

Easy to use

Our core is compact and implements standard interfaces, so it can be used easily either as a standalone block, or as part of a Qsys system. Again : it does not require any embedded processor. It is small and efficient enough to fit easily in low cost and small FPGAs, like in the Intel Cyclone III, Cyclone IV or Cyclone V families.

The core can be used as stand-alone block or with Qsys, with or without the Altera Video IP suite (“VIP”).

Our simulation environment can be helpful to develop and the application that includes the JPEG encoder.

This core has been used (with the corresponding JPEG Decoder) in a very successful consumer product.

Main Technical characteristics

Speed and Area-Optimized encoder engine suitable for both still image and real-time video compression.
8 bits (byte) Streaming output interface with Backpressure. Easy to connect to the ALSE Ethernet communication engine for example. Output format is 8x8 YUV Blocks (4:2:2).
Supports any image resolution up to 64k x 64k.
Suitable for still image and real-time video (streaming).
The core can accept close to 1 pixel per clock cycle.
Standard Huffman table.
Dynamically configurable Quantization tables (up to 8 tables) for multiple levels of compression and quality.
Dynamic choice of compression level (can be adjusted automatically).
Can be easily integrated in a complete video system using the ALSE “Block to Raster” module, a Memory Frame Buffer and a Video Output Controller (RGB outputs for VGA, LCD; YUV BT656, etc … )
Versatile. This IP can be used in all FPGA devices (internal memory blocks must be available).
Compact. On an Altera Device, the area is typically less than 3,300 Logic Elements, 5 memory blocks (M9K) and 9 DSP18-bits (multipliers) are used.
Fast : on an old Altera EP3C25F256C6 Cyclone III Device, the Encoder can run at more than 150 MHz.
First-class Technical Support (E-mail and Telephone, extended CET hours).
Customization to specific needs available.

Best in class

Some ALSE IPs also exist in the competition, JPEG Codec is in this case. However, our IP offers unique characteristics and advantages.

More compact.
More efficient than the competition.
Faster.

Demos available

We have many demos created for several FPGA boards, including our AVDB Video Development Board.

Information available

A datasheet is available, but do not hesitate to contact us if you want more details.

ALSE's JPEG Video Encoder is the smallest and most efficient IP to compress video in real time.

Graphic Display

2016-08-31T12:11:27Z

Objective

Deliver vivid and high quality graphics at the lowest possible cost.
Does not require a frame buffer nor external memory.

GraDiEn

GraDiEn: is a core Graphic Engine that can be tailored to many different applications, runs on very low cost FPGAs, and requires no frame buffer hence no external memory.
This IP is already used by customers in the automotive industry where cost certainly matters ! But any application can take advantage of our innovative and highly efficient technology.

The diagram below shows a typical application using GraDiEn.

Description

GraDiEn, the ALSE Graphic Display Engine, is a Ram-Less Sprite-based Graphic Display system designed to fit in extremely cheap hardware. It can be used to build Graphic Displays and User Interfaces for a lot of applications like Video Display control, Touch Screen driven GUIs, OSD (On Screen Display), Vending Machines, Industrial Control and display, etc … at the cost of a very cheap Bill Of Material.

With the emergence of mobile computing, small color LCD displays are now very inexpensive and GraDiEn fits in the smallest & low pin count FPGAs (no external volatile memory required), and therefore requires simple PCBs. Typically, only an external Flash memory and an oscillator need to be added to the FPGA and color LCD.

The controller can drive all kinds of screens with resolutions up to Full-HD (1920x1080p), but is of course perfectly suited to drive smaller resolutions such as QVGA (320x240), VGA, WXGA, etc… One advantage of the FPGA is the ability to adapt to virtually any kind of display interface (both physically and logically).

For some other designs, the FPGA will nicely complement an existing low cost micro-controller. This (optional) Processor can drive GraDiEn through any kind of link including: RS232, SPI, i2C, CPU or DSP bus, embedded CPU (wishbone or Avalon eg) etc… Some applications can drive the Graphic Engine internally (like Vending machines) without a processor. GraDiEn is also a good companion for an embedded processor (Nios II or other). The Sprites (icons, or static graphic objects) are stored in a non-volatile (external) memory, like Parallel Flash or Serial Flash (EPCS, SPI, Quad SPI…). Dynamic text and dynamic sprite are stored in the FPGA's internal memory.

Using Serial Memories help reduce the pin count and footprint but their bandwidth is usually inferior to modern burst-mode parallel memories. Note that we have developed a range of High-Performance Memory Controllers to take advantage of the modern and faster Flash memories, like the new Quad-SPI Flash devices.

The image and the graphic objects can be coded on 8, 16, or 24 bits. And 8 bits can be expanded to 24-bits using Look-up Tables.

GraDiEn Main features

Ram-Less (no external volatile memory is needed).
Includes a customizable LCD/VGA Display Controller that can support most Screen Resolutions (QVGA, VGA, WXGA, … up to Full-HD), with a Frame Rate up to 60 Hz.
Extremely compact (typically under 1,500 Logic Elements, depends on options, screen resolution and configuration).
Alpha Blending
Transparency
4 x “Z” levels
Dynamic Sprite (built “on the fly” by the application)
Dynamic Text Applet
Utility Programs included (to create and manage the graphical objects stored in Flash).
Optional Flash Programmer to update the Flash contents in-site, from the external controller.
Many demos available.
Simple commercial model (no Royalty).

The IP is available on all kinds of FPGAs provided they offer enough internal memory blocks. A lot of demo platforms are readily available (one for the Altera NEEK Kit is available directly on the web site).

Typical integration in a design usually takes less than one day.

If you want more information, fill in our Information Request Form and tell us what FPGA & screen resolution you plan to use.

Ask for our Full HD Demo on NEEK !