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	<title>A.L.S.E the FPGA Experts</title>
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	<description>A.L.S.E: Advanced Logic Synthesis for Electronics, offers a complete range of Services, IPs, Training courses and Boards to help you with the design of FPGA-based and EmbeddedSystems.</description>
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		<title>The ALSE AVB Milan IP</title>
		<link>http://www.alse-fr.com/The-ALSE-AVB-Milan-IP.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/The-ALSE-AVB-Milan-IP.html</guid>
		<dc:date>2024-01-25T15:21:16Z</dc:date>
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		<dc:language>en</dc:language>
		
		



		<description>
&lt;p&gt;In 2024, ALSE launched an FPGA IP for Milan, thus allowing any company to develop products incorporating the MILAN technology and protocols in record time, with very low effort, and guaranteed performance and compliance. The Milan IP sold and supported by ALSE is (by far) the most complex in the ALSE portfolio. It represents a lot of Years x Men of extremely challenging engineering. Re-designing this IP would represent an investment and a Time-to-Market delay that would simply be (&#8230;)&lt;/p&gt;


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&lt;a href="http://www.alse-fr.com/-AVB-MILAN-.html" rel="directory"&gt;AVB MILAN&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;In 2024, &lt;strong&gt;ALSE launched an &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; &lt;abbr title=&#034;Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc&#8230; Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.&#034;&gt;IP&lt;/abbr&gt; for Milan&lt;/strong&gt;, thus allowing any company to develop products incorporating the MILAN technology and protocols in record time, with very low effort, and guaranteed performance and compliance.&lt;/p&gt;
&lt;p&gt;The Milan IP sold and supported by ALSE is (by far) the most complex in the ALSE portfolio. It represents a lot of Years x Men of extremely challenging engineering. Re-designing this IP would represent an investment and a Time-to-Market delay that would simply be unrealistic, even for major companies.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;h2 class=&#034;spip&#034;&gt;The ALSE Milan &lt;abbr title=&#034;Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc&#8230; Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.&#034;&gt;IP&lt;/abbr&gt;&lt;/h2&gt;
&lt;p&gt;This IP combines a complex &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; &lt;strong&gt;Hardware design&lt;/strong&gt; (&lt;abbr title=&#034;Register Transfer Level. Simply put: it's HDL code that is suitable for synthesis. Which mean in practice describing what happens on rising edges of a Clock.&#034;&gt;RTL&lt;/abbr&gt;) located in the programmable side of the SoC-FPGA and a &lt;strong&gt;Software stack&lt;/strong&gt; that runs on the ARM Multi-Processor Core System of the same FPGA. This combination takes advantage of the FPGA Programmable Logic parallel processing to take care of very low latency and hard real time features like Ethernet packet processing (audio streaming), and uses the ARM Processor System to implement complex network management protocols in a very flexible way.&lt;/p&gt;
&lt;p&gt;The IP is currently available on the Intel Cyclone V &lt;abbr title=&#034;System On Chip. Usually a chip that contains one (or several) microprocessors on the die, as well as other logic. A SOC-FPGA is an FPGA that has Hard Core Processor(s) tied to the programmable logic.&#034;&gt;SOC&lt;/abbr&gt; FPGA family.&lt;/p&gt;
&lt;p&gt;For evaluation or for rapid prototyping, the IP is also available as a ready-to-use Module.&lt;/p&gt;
&lt;p&gt;We plan to provide more information about the architecture of the IP in this section. &lt;br class='manualbr' /&gt;However, signing a mutual Non Disclosure Agreement will be required to obtain all the details.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;The Milan AVB64M Module&lt;/h2&gt;
&lt;p&gt;Unlike other ALSE IPs that are essentially immaterial, the Milan IP is &lt;strong&gt;also&lt;/strong&gt; available under the form of a small, well documented, and ready-to-use &lt;strong&gt;Milan SoM&lt;/strong&gt; (System on Module).&lt;/p&gt;
&lt;p&gt;The AVB64M Milan Module has passed the MILAN Certification.&lt;/p&gt;
&lt;p&gt;This module is perfect for Evaluation with the ALSE Carrier board, and for prototyping purposes.&lt;/p&gt;
&lt;div class='spip_document_190 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;28&#034; data-legende-lenx=&#034;&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH238/avb64m_pic-387ab.jpg?1782755773' width='500' height='238' alt='' /&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-190 '&gt;&lt;strong&gt;Milan AVB System On Module
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;Quick summary of the AVB64M SoM features :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; SODIMM extended form, module TDP &lt; 5 Watts&lt;/li&gt;&lt;li&gt; TDM Audio interfaces : 64 in + 64 out / 48 kHz or 96 kHz clocks&lt;/li&gt;&lt;li&gt; 16 input audio streams (Avtp Audio Format, up to 8 channels per stream)&lt;/li&gt;&lt;li&gt; 16 output audio streams (AAF, up to 8 channels per stream)&lt;/li&gt;&lt;li&gt; 1 input clock stream (CRF = Clock Reference Format)&lt;/li&gt;&lt;li&gt; 1 output clock stream (CRF)&lt;/li&gt;&lt;li&gt; Media Clock master/slave capability&lt;/li&gt;&lt;li&gt; Redundancy or Bridge mode &lt;strong&gt;AVB network switch&lt;/strong&gt; (4 x 1 GB Ethernet ports)&lt;/li&gt;&lt;/ul&gt;&lt;h2 class=&#034;spip&#034;&gt;LaScala : the Milan SoM Carrier Board&lt;/h2&gt;
&lt;p&gt;To further speed up the development of products using the AVB64M SoM module, ALSE has developed the &lt;strong&gt;MILAN SoM Carrier Board&lt;/strong&gt;. It comes equipped with a Milan SoM module, a Reference Design for the board's FPGA, and with the complete schematics.&lt;br class='manualbr' /&gt;You can start designing and testing Audio products immediately, without waiting for the development of a custom board.&lt;/p&gt;
&lt;div class='spip_document_191 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;35&#034; data-legende-lenx=&#034;x&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/jpg/la_scala.jpg' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/jpeg&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH165/la_scala-c9158.jpg?1782755773' width='500' height='165' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-191 '&gt;&lt;strong&gt;LaScala : MILAN SoM Carrier Board
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;The Carrier board is designed to be used autonomously, but it can also be plugged in a PC (PCIe Gen2x1).&lt;/p&gt;
&lt;p&gt;The schematics of this carrier board as well as the code of the on-board FPGA are provided. This allows users to master quickly the Milan IP and start prototyping their own products in a very short time.&lt;/p&gt;
&lt;p&gt;The LaScala carrier board offers :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; A Cyclone V FPGA (no processor inside)&lt;/li&gt;&lt;li&gt; Hosts the AVB64M Milan SODIMM Module&lt;/li&gt;&lt;li&gt; 2 x Gigabit Ethernet RJ45 Ethernet connectors&lt;/li&gt;&lt;li&gt; Word Clock In + Out (SMB),&lt;/li&gt;&lt;li&gt; on board CS2000 PLL&lt;/li&gt;&lt;li&gt; MADI in + MADI out (SMB)&lt;/li&gt;&lt;li&gt; AES3 inputs + outputs (HE10 2x5)&lt;/li&gt;&lt;li&gt; High End Stereo ADC with inputs (Jack 6.35mm)&lt;/li&gt;&lt;li&gt; High End stereo DAC with headphones Jack (6.35mm)&lt;/li&gt;&lt;li&gt; 2 x USB UARTs&lt;/li&gt;&lt;li&gt; AudioPrecision Debug Connectors&lt;/li&gt;&lt;li&gt; TDM interfaces (Tx + Rx HE10 1.27 2x10)&lt;/li&gt;&lt;li&gt; TPM secure module&lt;/li&gt;&lt;li&gt; 4 x LEDs, 2 x Push Buttons, 4 x DIPsw&lt;/li&gt;&lt;li&gt; PCIe Gen1 x 1&lt;/li&gt;&lt;li&gt; External or PCIe Power Supply&lt;/li&gt;&lt;/ul&gt;&lt;h2 class=&#034;spip&#034;&gt;Add Milan-AVB to your products &lt;em class=&#034;spip&#034;&gt;today &lt;/em&gt; !&lt;/h2&gt;
&lt;p&gt;Here is the typical scenario to add MILAN-AVB support to your products.&lt;/p&gt;
&lt;ol class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Start by acquiring know-how on using the IP thanks to our low-cost prototyping bundle :&lt;br class='manualbr' /&gt;Carrier Board + AVB64M Module + prototype License&lt;/li&gt;&lt;li&gt; If desired, you can modify an existing product by adding a SODIMM socket to host an AVB64M module and connect it to your TDM channels and add two GB Ethernet (Milan-AVB) ports.&lt;/li&gt;&lt;li&gt; The following step will be to design your next product by integrating all the MILAN IP hardware on your board (basically by copying the main elements of the AVB64M module, all the information is passed to you).&lt;/li&gt;&lt;/ol&gt;
&lt;p&gt;Looks simple ? It is !&lt;/p&gt;
&lt;p&gt;If you are interested in the Milan IP, the SoM module or the Carrier Board, contact ALSE.&lt;/p&gt;&lt;/div&gt;
		
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<item xml:lang="en">
		<title>What is AVB MILAN ?</title>
		<link>http://www.alse-fr.com/What-is-AVB-MILAN.html</link>
		<guid isPermaLink="true">http://www.alse-fr.com/What-is-AVB-MILAN.html</guid>
		<dc:date>2024-01-25T15:21:13Z</dc:date>
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		<dc:language>en</dc:language>
		
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		<description>
&lt;p&gt;This section and its articles are dedicated to the technology of distributing real-time media contents over Ethernet and more specifically : Audio. We present briefly AVB and MILAN since we are launching in 2024 and AVB-Milan IP. AVB AVB &#8220;Audio Video Bridging&#8221; is a set of six IEEE standards that was first published in 2011 contributing to enable synchronisation and reliable, high-priority delivery of audio and video over Ethernet. However, this bundle of standards was not adequate (&#8230;)&lt;/p&gt;


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&lt;a href="http://www.alse-fr.com/-AVB-MILAN-.html" rel="directory"&gt;AVB MILAN&lt;/a&gt;


		</description>


 <content:encoded>&lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH85/milan-0aa92.jpg?1782755773' class='spip_logo spip_logo_right' width='150' height='85' alt=&#034;&#034; /&gt;
		&lt;div class='rss_chapo'&gt;&lt;p&gt;This section and its articles are dedicated to the technology of distributing real-time media contents over Ethernet and more specifically : Audio.&lt;/p&gt;
&lt;p&gt;We present briefly AVB and MILAN since we are launching in 2024 and AVB-Milan &lt;abbr title=&#034;Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc&#8230; Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.&#034;&gt;IP&lt;/abbr&gt;.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;h2 class=&#034;spip&#034;&gt;AVB&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;&lt;a href=&#034;https://en.wikipedia.org/wiki/Audio_Video_Bridging&#034; class=&#034;spip_out&#034; rel=&#034;external&#034;&gt;AVB&lt;/a&gt;&lt;/strong&gt; &#8220;Audio Video Bridging&#8221; is a set of six IEEE standards that was first published in 2011 contributing to enable synchronisation and reliable, high-priority delivery of audio and video over Ethernet.&lt;/p&gt;
&lt;p&gt;However, this bundle of standards was not adequate in practice to achieve practical interoperability among the various developers and manufacturers.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;MILAN&lt;/h2&gt;&lt;div class='spip_document_184 spip_document spip_documents spip_document_image spip_documents_right spip_document_right spip_document_avec_legende' data-legende-len=&#034;7&#034; data-legende-lenx=&#034;&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/jpg/milan.jpg' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/jpeg&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH283/milan-328f1.jpg?1782755773' width='500' height='283' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-184 '&gt;&lt;strong&gt;MILAN
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;&lt;strong&gt;Milan&lt;/strong&gt; has started in 2016 as a profile that guarantees interoperability of AVB audio devices in the market. It is a standards-based, user-driven deterministic network protocol for professional media, that assures devices will work together at new levels of convenience, reliability and functionality. &lt;br class='manualbr' /&gt;Milan has been created and is maintained by Pro Audio market leaders in the &lt;strong&gt;&lt;a href=&#034;https://avnu.org/&#034; class=&#034;spip_out&#034; rel=&#034;external&#034;&gt;Avnu Alliance&lt;/a&gt;&lt;/strong&gt;, and it is the first tangible solution for promising deterministic, reliable, and future-proof delivery of networked media. &lt;br class='manualbr' /&gt;Milan combines the technical benefits of the AVB standard with Pro AV market-defined device requirements at both the network and the application layer for media streams, formats, clocking and redundancy.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;AVDECC Library&lt;/h2&gt;
&lt;p&gt;Avnu member, &lt;strong&gt;&lt;a href=&#034;https://www.l-acoustics.com/about-us/discover-l-acoustics/&#034; class=&#034;spip_out&#034; rel=&#034;external&#034;&gt;L-Acoustics&lt;/a&gt;&lt;/strong&gt; (a French company and industry leader in the design, manufacturing, and distribution of premium sound reinforcement technologies) has published in 2019 an open source, free-to-use &lt;a href=&#034;https://github.com/L-Acoustics/avdecc&#034; class=&#034;spip_out&#034; rel=&#034;external&#034;&gt;AVDECC Library&lt;/a&gt; that is now fully Milan compatible with the recently published Milan Discovery, Connection &amp; Control Specification for Listeners &amp; Talkers. &lt;br class='manualbr' /&gt;With this specification, Milan delivers a clear, defined profile for devices with a small subset of the standard and removes all ambiguities from this subset in order to achieve interoperability at the control layer. &lt;br class='manualbr' /&gt;The open source library offers a set of tools for controlling AVB and Milan devices using the AVDECC (IEEE1722.1) protocol and to meet Avnu Milan specifications. &lt;br class='manualbr' /&gt;These libraries can be implemented on Windows, Linux and macOS using standard development tools. &lt;br class='manualbr' /&gt;Unit tests and sample programs are also available. &lt;br class='manualbr' /&gt;The open source tools are available today on GitHub.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Avnu Alliance&lt;/h2&gt;
&lt;p&gt; &lt;em class=&#034;spip&#034;&gt;&#8220;Reliable Synchronized Networking&#8221;&lt;/em&gt;&lt;/p&gt;
&lt;div class='spip_document_185 spip_document spip_documents spip_document_image spip_documents_right spip_document_right spip_document_avec_legende' data-legende-len=&#034;6&#034; data-legende-lenx=&#034;&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='http://www.alse-fr.com/sites/alse-fr.com/IMG/jpg/avnu.jpg' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/jpeg&#034;&gt; &lt;img src='http://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH114/avnu-83a50.jpg?1782755773' width='500' height='114' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-185 '&gt;&lt;strong&gt;Avnu
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;
&lt;p&gt;&lt;a href=&#034;https://avnu.org/&#034; class=&#034;spip_out&#034; rel=&#034;external&#034;&gt;Avnu Alliance&lt;/a&gt; is a transformative force in the world of real-time networking. &lt;br class='manualbr' /&gt;Established in 2009 by experts from diverse fields such as networking, IT, professional media, and automotive, the Avnu Alliance goal has been clear and consistent: to promote and facilitate the rapid, widespread, and open industry adoption of standards-based networking for time-sensitive, highly reliable applications.&lt;/p&gt;
&lt;p&gt;Avnu Alliance has built a robust &lt;strong&gt;Certification&lt;/strong&gt; program, which is key to guarantee seamless interoperability of various products.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;ALSE&lt;/strong&gt; is now part of the Avnu Alliance as &lt;strong&gt;Milan Associate&lt;/strong&gt;.&lt;/p&gt;&lt;/div&gt;
		
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