A.L.S.E the FPGA Experts

SDI on Lattice

2026-07-23T15:32:01Z

The Lattice Nexus platform offers a combination of advantages that allow these FPGAs to address efficiently a number of difficult applications, especially in the small footprint + low power + low cost constraints.

We have successfully ported our SDI to this platform and addressed a challenging application.

For a customer's project, we had to design an interface between an SDI color camera and a battery-powered system we designed for an IR sensor, fitting inside a very small PCB. Some video processing also needed to fit in the FPGA, and indeed the power budget needed to be as low as possible.

We found that a Lattice CertusPro NX could be a nice fit.
But the https://en.wikipedia.org/wiki/SerDes]. _ Most recent FPGAs now offer a number of SERDESes allowing to stream data in and out of the FPGA serially at very high speeds. Moreover, recent connectivity protocols like PCIExpress, HDMI, DisplayPort etc make use of SERDESes.">SERDES Supported Standards table (page 55) doesn't include SDI.
After exchanging and getting help from the Lattice Engineering team, we had very good hopes and we decided to port and test our SDI IP on the CertusProNx.

The port went well : all our tests have passed with flying colors, and this bridge runs at a very low power. This FPGA and our IPs were an efficient combination to solve a challenging problem and offer a lot of flexibility.

We will demonstrate this IP on our future ALSE CertusProNx Development kit that will be announced and available in September.

Aurora on Avant !

2025-10-27T17:28:40Z

Discover how you can create an inter-FPGA Aurora link on the latest Lattice FPGA families.

In 2025, the Lattice Avant™ 16nm FinFET platform became available.
Taking advantage of its know-how in terms of low cost and low power consumption, Lattice now enters the mid-range FPGA market with state-of-the-art silicon.

The Avant™ families offers a faster fabric and numerous high-speed transceivers channels (up to 28 channels at 25 Gbps for the largest Avant-X) that are reaching FPGA NRZ transceiver's high boundary.

At ALSE we have a long history of working with practically all the FPGA vendors and families, and by consequence with all types of FPGA transceivers. We have developed many transceiver-based IPs including : HDMI, SDI, JESD204b, Gedek (100M/1G Ethernet), 10GEDEK (10G Ethernet), Aurora 8B/10B, and Aurora 64B/66B !

Therefore, having gained an early access to a brand new Lattice Avant-G Versa board, we could not resist to tryout this new FPGA family by porting our Aurora IPs on this platform.

In this Application Note we demonstrate a Reference Design based on our Aurora 8B/10B IP ported on the Lattice Avant families.

Note that our Aurora 64B/66B IP is also available on Avant™.
If all goes well you'll see a demo running on the Lattice booth at Embedded World.

Read our Application Note below.

ALSE Aurora 8B/10B on Efinix

2025-08-21T15:18:05Z

We have ported our Aurora 8B/10B on Efinix Titanium.

We have built a nice and convincing demo based on the Efinix Titanium kit.
This demo is described in the document below.

ALSE Aurora8b10b on Efinix Titanium : Demo User Guide

In principle, this type of document is confidential and accessible only after signing a mutual NDA.
Please understand that you have no right to copy or distribute it by any means.

ALSE Aurora 64B/66B on Efinix

2025-08-21T15:17:49Z

We have ported our Aurora 64B/66B on Efinix Titanium.

We have built a nice and convincing demo based on the Efinix Titanium kit.
This demo is described in the document below.

ALSE Aurora64 Demo on Efinix Titanium

In principle, this type of document is confidential and accessible only after signing a mutual NDA.
Please understand that you have no right to copy or distribute it by any means.

MachXO5 Example Design

2025-04-27T17:57:58Z

A very long time ago, we (A.L.S.E.) have invented the concept of a processor-less Ethernet stack !
We named the IP “GEDEK” for Gigabit Ethernet Data Exchange Kit and it has since helped a lot of customers to implement high speed data transfers in their FPGA designs using minimal resources.

This Reference Design shows an application where a small FPGA (the MachXO5-25) can host 14 independent I2C controllers running in parallel, while ensuring bi-directional data transfer with a PC through Ethernet, within a fraction of the FPGA resources.

If you own the MachXO5T-NX Development Board or the MachXO5-NX Development board (Ethernet version), you can quickly test our Reference Design.

I2C & Ethernet Reference Design Principle

A Lattice MachXO5T-NX development board or MachXO5-NX development board is used with up to 4 x Pmod I2C Temperature sensors attached.
Each PMOD connector can host two sensor modules.
The design configures the sensors in their most accurate (and slowest) mode (12 bits with a resolution of 1/16^th Celsius). The sensors are read 4 times per second.

The LEDs can display the LSBits of Sensor 0 temperature, or a value written by the PC.
The LEDs are dimmed by a PWM which can be adjusted by the PC.
We provide a Python utility program : i2c_eth.py to exercise the FPGA.
We also provide a command line utility gedek_rw.exe to read and write in the FPGA register map.

The utility programs are available for Windows and Linux.

Block Diagram of the Reference Design

BlockDiagram

MachXO5T board

The commercial reference of this board is LFMXO5-100T-EVN. The documentation can be found here.

MachXO5T-NX evaluation board

MachXO5-NX board

The MachXO5™-NX Development Board, has a smaller FPGA (-25 instead of -100) and is available in two versions with and without Ethernet ! You need this reference : LFMXO5-25-E-EVN (with Ethernet support). The documentation can be found here.

MachXO5-NX board

Testing the Reference Design

All the details can be found in the document below.
You will see how to connect temperature sensors, program the board, connect it to Ethernet and interact with the board from your PC through Ethernet. You'll see how to visualize the Ethernet frames exchanged using Wireshark.

If you own a LFMXO5-100T-EVN board or a LFMXO5-25-E-EVN board, please contact us so we can send you the latest archive to test this Reference Design.

Discovering Radiant

2025-01-31T08:51:03Z

Lattice offers several families of FPGAs that are attractive for many applications.
If you want to discover and evaluate quickly the latest Lattice development tool, “Radiant”, this article will help you retrieve, install, license and use Radiant in no time, at no cost !

/!\ Important… Radiant 2026.1 is now available, with many improvements. Install this latest version.

The document below does describe, step-by-step, how to :

Retrieve Radiant installation for Windows or Linux
Install Radiant
License Radiant (free)
Prepare your Windows or Linux environment
Launch Radiant and associated tools
Create a simple project from scratch
Compile the FPGA
Discover the main steps of the design flow
Perform simulations
Attend a free Lattice video training to dig deeper into Radiant features.

If you have some practice designing FPGAs and follow the steps, you should be able to quickly start a real-world project with Radiant.

You will find all you need in the pdf document below.

DSP in Lattice FPGAs (1)

2025-01-30T09:33:30Z

This Application note, the first of a series, demonstrates how to take advantage of the hardware resources in Lattice FPGAs to implement Digital Signal Processing functions efficiently.

We created this Application Note after having designed a dedicated and very optimized Large FIR Filter IP for a customer. We ran into issues and it took us some effort to properly use the Lattice tools and converge on an efficient methodology to take advantage of the sysDSP blocks that are available in most Lattice FPGAs.

This application note (pdf) can be downloaded below. We created also an archive (zip), which contains also the design files, the testbenches, simulation scripts and a Radiant project. You can download it from this link.

If you are not yet familiar with Radiant and would like to test the methodology described in our document, contact us to receive our “Quick Radiant Installation Guide with First Steps”.

Good reading !

Happy New Year

2025-01-08T08:26:27Z

Best Wishes from ALSE

The A.L.S.E Team in France wishes you all the best for 2026…
… and will be at your side for your Digital Projects
with our (FPGA & ASIC) IPs, our Design Services,
our Expertise and our Trainings !

High-Speed JPEG Video Encoder

2024-12-31T10:46:55Z

This is a “dual-core” version of our standard JPEG encoder.
It is still compact enough and efficient to fit in a very small low cost FPGA while allowing real time compression at higher resolutions than Full-HD at 60fps.
It has an option to generate a video stream optimized for GPU decoding ! This is a unique feature on the market, now tested and used on high-end commercial products.
This IP does not require any processor nor any external memory.

Purpose

This “Dual-Core” High-Speed Baseline JPEG Encoder (Compression) core is capable of encoding video on-the-fly while producing standard JPEG compressed format. Its “Dual-core” architecture doubles the compression speed as compared to our standard baseline JPEG Encoder. The use of JPEG compression allows using very small FPGAs without external memory, leading to very economical systems, and our dual-core architecture allows high resolution and frame rates compression on low cost FPGAs.

Architecture

ALSE HighSpeed (dual-core) JPEG Encoder

Easy to use

Our core is compact and implements standard interfaces, so it can be used easily either as a standalone block, or as part of a Platform Designer system (or equivalent).

Again : it does not require any embedded processor nor external memory. It is small and efficient enough to fit easily in low cost and small FPGAs, like in the Altera Cyclone and Agilex 3 families, or the Lattice FPGA families (eg ECP3, ECP5, Certus-NX, CertusPro-NX, Crosslink-NX, Mach-XO5 etc) or the Microchip FPGAs (Igloo 2 or Polarfire).

It fits (indeed) very well in higher-end families (Altera Agilex 5 or Agilex 7, Lattice Avant-X and Avant-G etc), thus offering the capability to support high resolutions and frame rates. Our simulation environment can be helpful to develop and the application that includes the JPEG encoder.

Main Technical characteristics

Speed and Area-Optimized encoder (dual-core) engine
Suitable for both still image and real-time video compression.
8 bits (byte) Streaming output interface with Backpressure. Easy to connect to the ALSE Ethernet communication engine for example. Output format is 8x8 YUV Blocks (4:2:2).
Option to generate a video stream optimized for multi-thread GPU decoding !
Supports any image resolution up to 64k x 64k.
Standard Huffman table.
Dynamically configurable Quantization tables (up to 8 tables) for multiple levels of compression and quality.
Dynamic choice of compression level (can be adjusted automatically).
Can be easily integrated in a complete video system using the ALSE “Block to Raster” module, a Memory Frame Buffer and a Video Output Controller (RGB outputs for VGA, LCD; YUV BT656, etc … )
Versatile. This IP can be used in all FPGA devices (internal memory blocks must indeed be available).
Compact.
Fast : excellent Fmax on all FPGA families.
First-class Technical Support (E-mail and Telephone, extended CET hours).
Customization to specific needs is possible.
Verification Environment with advanced test benches.

Best in class

Some ALSE IPs also exist in the competition, JPEG Codec is in this case. However, our IP offers unique characteristics and advantages.

More compact.
More efficient than the competition.
Faster (better Fmax).
Dual-engine version.
Optimized for multi-thread decoding (GPU) -encoder option-.

Demos available

We have many demos created for many FPGA boards.

Trainings outside Europe

2024-07-19T07:33:31Z

Since most of our Training courses are now delivered Live OnLine, we can reach many parts of the world with an adapted format (typically: shorter daily sessions).

Specifically when you have a Team to train, it might make sense to check with us if we can help you efficiently.
Don't worry : if we think the training won't be optimal for any reason, we will quickly tell you ! We are always very busy (since our engineers are first active designers) and our time is as precious as yours.

But we know and teach things that you will probably not find anywhere else. If that's what you're looking for, we will do our best to share our know-how, even if we are not in the same timezone.

If you would like to organize a training outside Europe, please contact us.

You can also tell us which Training(s) you are interested in