{"version":"1.0","type":"rich","provider_name":"A.L.S.E \u003Csub\u003Ethe \u003Cabbr title=\"Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.\"\u003EFPGA\u003C\/abbr\u003E Experts\u003C\/sub\u003E","provider_url":"https:\/\/www.alse-fr.com","title":"8254","author_name":"Jacques Pyrat","width":"480","height":"295","url":"https:\/\/www.alse-fr.com\/8254-Programmable-Timer-Counter.html","html":"\u003Ch4 class='title'\u003E\u003Ca href='https:\/\/www.alse-fr.com\/8254-Programmable-Timer-Counter.html'\u003E8254\u003C\/a\u003E\u003C\/h4\u003E\u003Cblockquote class='spip'\u003E\n\u003Cp\u003EWe have designed a synchronous but limited RTL model of the Intel 8254  Programmable Timer \/ Counter. \n\n We have used this model in combination with the model of the 6809 CPU to re-design a complete obsolete industrial board into an FPGA. \n\nOur 8254 model is currently not exhaustive: we have only modeled and tested the functions that were used in the design. \n\nIt\u2019s typically easy to verify how the 8254 was used, and make sure the RTL model will behave adequately. \n\nIf you are interested in (\u2026)\u003C\/p\u003E\n\u003C\/blockquote\u003E\n"}