https://www.alse-fr.com/ A.L.S.E: Advanced Logic Synthesis for Electronics, offers a complete range of Services, IPs, Training courses and Boards to help you with the design of FPGA-based and EmbeddedSystems. en SPIP - www.spip.net https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L144xH42/siteon0-d414d.png?1782755771 https://www.alse-fr.com/ 42 144 https://www.alse-fr.com/UVM-Adopter-78.html https://www.alse-fr.com/UVM-Adopter-78.html 2016-09-11T16:39:18Z text/html en <p>Complete 4-days <abbr title="Universal Verification Methodology. The convergence of many different vendor-specific Methodologies and the only one that is here to stay. It is based on SystemVerilog and especially the Classes (OOP) part of it. UVM is hard to learn and master.">UVM</abbr> training. <br class='manualbr' />/!\ beware of pre-requisites though !</p> - <a href="https://www.alse-fr.com/-Agenda-.html" rel="directory">Agenda</a> <div class='rss_chapo'><p><a href="http://www.alse.fr/Formations/formations-FPGA/UVM_4j-adopter-class.html" class="spip_out" rel="external">Consult the French Trainings article</a></p></div> https://www.alse-fr.com/SystemVerilog-Verification-Classes.html https://www.alse-fr.com/SystemVerilog-Verification-Classes.html 2016-09-11T16:28:10Z text/html en <p>This training follows “SystemVerilog for Design” and precedes the “UVM” training. Consult the French Trainings article</p> - <a href="https://www.alse-fr.com/-Agenda-.html" rel="directory">Agenda</a> <div class='rss_chapo'><p>This training follows “<abbr title="SystemVerilog (IEEE standard 1800) is an HDVL (Hardware Description &#38; Verification Language). _ This is the Language that now supersedes both Verilog and VHDL, thus becoming the de facto Language of the next 20 years.">SystemVerilog</abbr> for Design” and precedes the “<abbr title="Universal Verification Methodology. The convergence of many different vendor-specific Methodologies and the only one that is here to stay. It is based on SystemVerilog and especially the Classes (OOP) part of it. UVM is hard to learn and master.">UVM</abbr>” training.</p></div> <div class='rss_texte'><p><a href="http://www.alse.fr/Formations/formations-FPGA/systemVerilog_Classes.html" class="spip_out" rel="external">Consult the French Trainings article</a></p></div> https://www.alse-fr.com/FastTrack-Verilog.html https://www.alse-fr.com/FastTrack-Verilog.html 2016-09-11T16:17:07Z text/html en <p>Consult the French Trainings article</p> - <a href="https://www.alse-fr.com/-Agenda-.html" rel="directory">Agenda</a> <div class='rss_texte'><p><a href="http://www.alse.fr/Formations/formations-FPGA/fast-track-verilog.html" class="spip_out" rel="external">Consult the French Trainings article</a></p></div> https://www.alse-fr.com/Comprehensive-VHDL.html https://www.alse-fr.com/Comprehensive-VHDL.html 2016-09-11T14:15:38Z text/html en <p>This is a 5-days (3+2) modular VHDL Training Course.</p> - <a href="https://www.alse-fr.com/-Agenda-.html" rel="directory">Agenda</a> <div class='rss_chapo'><p>This is a 5-days (3+2) modular <abbr title="VHSIC Hardware Description Language. _ A consequence of the US DOD's VHSIC program, this language (normalized as IEEE 1076) was created to describe accurately the behavior of High Speed Integrated Circuits.">VHDL</abbr> Training Course.</p></div> https://www.alse-fr.com/SystemVerilog-for-Design-on-site.html https://www.alse-fr.com/SystemVerilog-for-Design-on-site.html 2016-09-11T14:12:45Z text/html en <p>FastTrack Verilog (condensed in 1 day) followed by SystemVerilog for Design (3 days).</p> - <a href="https://www.alse-fr.com/-Agenda-.html" rel="directory">Agenda</a> <div class='rss_chapo'><p>FastTrack <abbr title="The first (in order of appearance) Hardware Description Language (like VHDL which followed a few years later). Normalized as IEEE 1364.">Verilog</abbr> (condensed in 1 day) followed by <abbr title="SystemVerilog (IEEE standard 1800) is an HDVL (Hardware Description &#38; Verification Language). _ This is the Language that now supersedes both Verilog and VHDL, thus becoming the de facto Language of the next 20 years.">SystemVerilog</abbr> for Design (3 days).</p></div>