A.L.S.E the FPGA Experts

Embedded Software

2016-09-27T15:09:22Z

With more and more complex and powerful Processor cores included in FPGAs, we have developed a deep competence in Embedded Systems and Embedded Software.
It covers from embedded Soft CPU Cores to ARM High Performance Systems. And indeed, beyond bare metal, we are have developed very strong competences in Embedded Linux.

Custom Board Support Packages

One of the biggest challenges when developing software targeting a soft core embedded in an FPGA (such as the Nios II) or a hardened ARM application-class processor (such as in the SoC-FPGA components) is taking into account the flexibility of the FPGA, which allows to implement a completely custom system on chip.

ALSE can develop a board support package (BSP) tailor-made for any custom system based on those technologies in a matter of days. Such a BSP is typically composed of a bootloader (U-Boot) and a Linux-based custom distribution, including a software development kit allowing the customer to develop in-house applications on top of this BSP.

We often use the Buildroot integration tool to generate our BSPs, as its set of features and ease of use are a good fit for a lot of small to medium-scale embedded Linux projects. However, we are indeed mastering and using Yocto. We also deliver Yocto trainings.

Custom peripherals and drivers

As highlighted above, an FPGA-based system is bound to contain some custom-made peripherals. To properly access those peripherals from a running Linux system, custom drivers are needed. Developing such a driver (including, of course, device tree awareness) is well within ALSE's competence range.

One example of a driver we commonly integrate is one which provides an easy and clean way for the applications running on the processor to exchange data with the FPGA.

The main appeal of our GEDEK IP is to be able to use Ethernet communication without any processor. However it also features a raw port, allowing a processor to use it as a “standard” MAC device, alongside the normal GEDEK operation. We've developed a driver allowing this feature.

Remote update

There is a common need in embedded systems to be able to update the application software. The usual embedded constraints mean that this is a non-trivial problem.

We implemented a generic solution to this need, with the following features:

Robustness against power cuts and failed upgrades;
Whole-system image updates;
- In contrast with a package manager, not safe in most embedded systems.
- In order to keep user data intact, overlay filesystem support can easily be added.
Customizable way to deliver the upgrade payload (through a web-server or any custom application);
Based on open-source components;
Able to validate signed images with OpenSSL.

Custom FPGA Design

2016-09-17T15:14:59Z

Designing FPGAs, or Complex Hardware functions, or Embedded Systems for our Customers is our #1 occupation !

In most cases, our customers are asking us to design the entire FPGA or Embedded System for them. With our rich internal know-how, very focused, expert and dedicated Design Team, allied with our excellent methodology, we are usually in the best position to do so.

Some other times, we design only Complex Blocks or IPs, for customers who have internal design competence but who need help on some functions, who experience design resource shortage, or who must deal with extremely short deadlines.

But in all situations, we are clearly different from other contractors, and quite proud of our Modus Operandi:

We transfer our know-how to our customers ! This is probably our most attractive peculiarity, and it changes the sub-contracting paradigm in a very positive way.
Our strong Training activity is clearly a plus, since we can make sure our customers acquire the right know-how to appropriate our work in the best conditions.
We quote firm delivery dates and prices, even if the specification is fuzzy or incomplete!
We guarantee that our design will work, reliably.
Many new customers are surprised to see that our designs are usually functional at first try. This is only the consequence of a very solid methodology, with a strong verification process based on simulation, behavioral models, etc…
As of reliability, this is where our expertise shines. But don't imagine we apply some well-kept secrets to achieve this quality: we actually teach all these safe design rules that make a difference ! You can then understand why a lot of the existing code that you can find is unsafe and unreliable.
We have a success rate of 100 %, and we want to stay there !
This Zero Failure figure has a great value for us, and we work hard to make sure we won't compromise it.
And indeed our deliveries are never late.
Payment occurs only when the design is finished (and working).
We normally do not quote up front fees.
We are extremely fast !
The design of a complete and quite complex FPGA is typically around three weeks. Sometimes even less.
We are (as a consequence of the above) normally much cheaper than the competition. But we can't guarantee this: some desperate or far contractors may quote very low prices and deliver designs that have no chance to work properly. By not transferring the know-how, they usually plan to invoice more after the initial delivery, and they often take advantage of holes in the specification.
Unfortunately, we have been called to fix these “designs” way too often and these practices are hurting the (serious) sub-contracting business.

So, clearly, we don't mind if we do not produce the cheapest quotation (though most of the time, we do), we want to remain the best partner and guarantee the customer's project success.

As you can easily discover, working with us is very easy, productive and safe. You just have to contact us with our contact form and tell us in a few words what your project is and how we could help you. Very quickly, we'll get back to you and -if we can help- you will receive within a few days a quotation for the service you need.

If we are not in the best position to help you, or if we think of other solutions in your own interest, we will tell you !

We do not chase customers, we never had to advertise, and we are always very busy. And indeed we want to keep our success rate at 100% so we are committed to succeed.

Remember :

We can design a complex FPGA in just 2 to 3 weeks !
If needed : we can also build a hardware prototype for you.
We act as a Team in your company and as a Partner committed to your Project's success.
With ALSE, your success is 100% guaranteed.
We will transfer our know-how, and we can train you if necessary.

More than 30 years of existence and 100% success rate can't lie !

Auditing & Reviews

2016-09-17T14:13:30Z

HDL Code and FPGA Design Reviews and Auditing are often welcome or required :

When an FPGA project is critical (or just important enough)
When reliability is a key issue.
When an FPGA fails to perform reliably in the field, or in a given production batch, or during reliablity tests.
When the design is subcontracted, to verify that quality requirements are met.
To get a slipping project back on tracks.
To estimate early the complexity of a design.
and many other circumstances …

Design Review and Auditing is not among our preferred tasks. It is not particularly creative, and it often means delivering bad news (customers suspecting they have a code quality issue are -alas- usually right in their suspicion).

Our preference is when we have trained enough engineers in the company so they can perform the review internally without involving us, but we acknowledge this is not always possible.

So we know Audits and Reviews can be very important to our customers, and we keep them in our list of available Services.

The better side of this is that we can always provide a solution ! We we can't guarantee the solution will please the customer (we often have to re-design at least parts of the project), but we normally can guarantee we will solve the problems !

If you would like us to review a project or some code, it's fairly straightforward :

If necessary, we sign an NDA (Confidentiality / nondisclosure Agreement) so you can send us confidential information as needed.
You send us the code of the project and the information to be used for the review (specification is appreciated !).
We quickly send back a commercial quotation (typically within 48 hours) that includes the price, the delay and the list of deliverables. Sometimes, we stop here when we consider that the code is a lost cause and can't be salvaged (with the widespread trend to outsource the design tasks to weird and faraway locations, this unfortunately happens).
Once you agree, we perform the review and at least two engineers will perform and consolidate it. A report is built and sent back.

The whole process typically takes only a few days and it has a potentially very high ROI due to our mastering of Safe Design Rules and all the previous Failures analysis we have conducted. We can (and often do) predict failures and we identify weaknesses in the design before they can actually hurt the project.

Sometimes, the review is motivated by and focused at detecting a design error to explain failures witnessed in a product (usually in the field).

Don't imagine that these “Post Mortems” always reveal very intricate issues: over 90% of the failures are due to the breaking of very fundamental Safe Design Rules… another Myth busted !

In any case, if you think you may need us : it does not cost asking.

Asic to FPGA

2016-08-31T13:06:34Z

In some cases, you may have an old ASIC that becomes obsolete. You cannot afford to redesign a similar ASIC, yet you would like to avoid redesigning the complete system(s) that were using it.
Another case is wanting to include the functions performed by an obsolete ASIC into a new design. _A possible solution to this kind of problems is to use what you can recover from the original ASIC specification and design an FPGA based on this.

At ALSE, we've performed this kind of job quite a few times already.

In some cases, a lot of the original ASIC specification was lost (but we got high level description and a netlist) , at other times we had more complete functional description as well as expected values based on known stimuli.

These projects were not trivial but all successful in the end. In one case, a tweaking phase was necessary to painfully re-create the bugs and limitations of the original ASIC (!) since they contributed to create enormous databases of data that were exploited by sophisticated algorithms that took into account the ASIC exact behavior.

It is certainly not among our most typical projects, but we've been there, done that ;-)

System09

2016-08-31T13:06:32Z

System09, a 6809-based complete system-on-FPGA, does defeat 6809 Obsolescence !

What is System09 ?

Based on the excellent work of John Kent, in Australia, we have built in 2007 a fully synchronous (rising_edge) and cleaned up version of his 6809 processor.

We have also updated his System09 platform, which is now target-independent and verified by test benches and behavioral models, and has been tested on several Altera boards.

We have used this port in an industrial design.

The 6809 CPU fits in 2200 Logic Elements. As a consequence, a complete CPU board with many (obsolete) peripherals and even some memory can fit in a single and small FPGA.
This has applications beyond the nostalgic hobbyists !

How can I try it ?

You can download the bitstream of this System that runs on the old and cheap Terasic DE1 kit (Cyclone II) and you can test it very easily :

Program the DE1 with the DE1_System09_bitstream (.sof file).
Plug a PS/2 keyboard (QWERTY !)
Connect a screen to the VGA connector
Optionally : connect an RS232 cable on the serial port with a PC as terminal. Configure the terminal program (PuTTY or Hyperterminal eg) for 57600 bauds, N81, and no handshake.

That's it ! LEDr9 should “beat”, indicating that our design is loaded, and you should see the message “K_BUGS9S V1.0” followed by a prompt on the screen.

You can now enter 6809 Monitor commands using the Keyboard.
Note that the LEDs (LEDr0..8) monitor a part of the CPU address bus.

Try entering the following command (UPPERcase, spaces optional):
E FE00 FFFF.

The serial (RS232) port is operational and you can debug and load compiled code using a PC as a terminal (with the “L” command).
With the serial port, you don't even need the keyboard nor the VGA display.

Interested ?

If you need to convert an obsolete system that used a 6809 FPGA, ALSE can do this for you ! We will analyze your board, and see what other components beyond the CPU we can convert into an FPGA. Most of the time, we can convert the external SRams, the old E2Prom memories, some CPU peripherals (UART, Timers, PIOs etc).

Please contact us if you want to evaluate the opportunity to redesign an obsolete board.

You can also read our small article about Obsolescence.

Z8030/8530

2016-08-31T13:06:29Z

We have developed a limited RTL model of the Zilog Z8030/8530 - SCC Serial Communication Chip. We used it in combination with the model of the obsolete 6809 CPU to re-design an obsolete industrial board into an FPGA.

Our model is currently not exhaustive: we have only modeled the UART (Asynchronous Serial communication functions) but not the Synchronous part. In other words, if your design uses the Synchronous mode, we don't have the right model off-the-shelf.

It's typically easy to verify how the chip was used and make sure the RTL model will behave adequately.

The features of our IP are :

Two Independent, 0 to 2M Bits/Second, Full Duplex Channels, each with a Separate Baud Rate Generator (see below about ext osc emulation).
Asynchronous Mode with 5 to 8 Data Bits and 1, 1.5, or 2 Stop Bits per character,
Programmable Clock Factor, Break Detection and Generation, Parity, Overrun, and Framing Error Detection. Three interrupts are implemented.
Local Loopback and Auto Echo Modes
Fully synchronous implementation.
Emulation of the external oscillators using the internal clock source (removes the need for external oscillators).
Same register Set as the original part for software compatibility (in Asynchronous communication mode).
Deliverables include complete RTL source code (VHDL) with test benches and behavioral models.

If you are interested in this model, let us know, we could complete it if necessary for your project.

8254

2016-08-31T13:06:27Z

We have designed a synchronous but limited RTL model of the Intel 8254 Programmable Timer / Counter.

We have used this model in combination with the model of the 6809 CPU to re-design a complete obsolete industrial board into an FPGA.

Our 8254 model is currently not exhaustive: we have only modeled and tested the functions that were used in the design.

It's typically easy to verify how the 8254 was used, and make sure the RTL model will behave adequately.

If you are interested in this model, let us know, we could complete it if necessary for your project.

PCA 9556 & 9557

2016-08-31T13:06:25Z

These devices were I²C I/O port extenders by Philips (now NXP).
We have developed RTL models so you can add these functions to any FPGA.

We have developed an optimized IP that implements the same functionality as the PCA 9556 and 9557, with the ability to handle more ports and to fit in very small Programmable devices (one implementation fits in an 240 Macrocells CPLD).

The function performed by these devices is :

Slave SMBus/ I²C Ports I/O Expander.

This function is not very complex, so we deliver this IP in source code mode so the user can freely customize and re-use it.

When the original device had one port, our IP can have many 8-bits ports, this is a parameter in the IP core.

Moreover, the Voltage Levels and I/O standards will be those available on the FPGA. While being potentially an issue if 5V is required, it is usually and advantage when other levels are required.

A Demonstrator is available.

Board and System Design

2016-08-31T13:02:42Z

Over the years, an increasing number of our clients asked us if we could design complex boards and systems for them.

Some companies did not maintain PCB design teams or did not acquire the increasingly complex competence required by modern PCBs with signals running at more than 10 GHz, huge SI (Signal Integrity) issues, routing challenges, and critical PCB technology.

We have listened to them.

At ALSE, we have one PCB and System Design Expert.

His 'Hall of Fame" since he joined us is our own boards (AVDB, Signal Acquisition module, HPPB, HPAPB) as well as many customer projects. Our last complex PCB (for HPAPB) uses 16 layers on Megtron6 substrate with buried and filled-in laser vias.

Our Expert is also good at designing FPGAs and complex systems like arrays of interconnected boards. Today, being an excellent FPGA designer is nearly a requirement for designing PCBs hosting the latest FPGA families.

His extremely wide experience covers Analog, High frequency, High Temperature PCBs, Manufacturing, and much much more…

At this time, we are still using Altium Designer as Schematics and PCB design software.

This being said, you can easily imagine that he is constantly busy (and overly so). This means our bandwidth is severely limited and we have to reserve his time for complex and valuable projects.
However we do not intend to hire a second PCB designer (our core competencies remain FPGA design and Embedded Systems, and both are more challenging every year), so there is no hope of seeing our bandwidth increasing drastically.

If you are facing a PCB design challenge, you can contact us, if only to get a free evaluation of the complexity and maybe a quotation for your PCB or board design.
In any case, it's better if you contact us early.