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	<title>A.L.S.E the FPGA Experts</title>
	<link>https://www.alse-fr.com/</link>
	<description>A.L.S.E: Advanced Logic Synthesis for Electronics, offers a complete range of Services, IPs, Training courses and Boards to help you with the design of FPGA-based and EmbeddedSystems.</description>
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		<title>A.L.S.E the FPGA Experts</title>
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		<title>ALSE History</title>
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		<dc:date>2016-09-09T19:55:57Z</dc:date>
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&lt;p&gt;This is the (now long) History of A.L.S.E ! Inception ALSE was created in 1993 by me (Bertrand Cuzeau) with the voluntary and benevolent help of my retired father (Jacques Cuzeau) who passed in 2010. ALSE mission was to promote new digital design tools and methodologies, and to introduce Synario (a new tool from Data I/O) in France. At that time, only ASIC designers used Verilog or VHDL synthesis and simulation, while Programmable Logic designers were stuck with primitive tools based (&#8230;)&lt;/p&gt;


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&lt;a href="https://www.alse-fr.com/-About-us-.html" rel="directory"&gt;About us&lt;/a&gt;


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 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;This is the (now long) History of A.L.S.E !&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;h2 class=&#034;spip&#034;&gt;Inception&lt;/h2&gt;
&lt;p&gt;ALSE was created in 1993 by me (Bertrand Cuzeau) with the voluntary and benevolent help of my retired father (Jacques Cuzeau) who passed in 2010.&lt;/p&gt;
&lt;p&gt;ALSE mission was to promote new digital design tools and methodologies, and to introduce Synario (a new tool from Data I/O) in France. &lt;br class='manualbr' /&gt;At that time, only &lt;abbr title=&#034;Application Specific Integrated Circuit. It is a Custom Design chip implementing usually many functions and designed by a customer. As opposed to Programmable devices or to ASSPs.&#034;&gt;ASIC&lt;/abbr&gt; designers used &lt;abbr title=&#034;The first (in order of appearance) Hardware Description Language (like VHDL which followed a few years later). Normalized as IEEE 1364.&#034;&gt;Verilog&lt;/abbr&gt; or &lt;abbr title=&#034;VHSIC Hardware Description Language. _ A consequence of the US DOD's VHSIC program, this language (normalized as IEEE 1076) was created to describe accurately the behavior of High Speed Integrated Circuits.&#034;&gt;VHDL&lt;/abbr&gt; synthesis and simulation, while Programmable Logic designers were stuck with primitive tools based on schematics using proprietary libraries, with first generation languages (Abel, Palasm, Cupl&#8230;) and with gate-level simulators (at best !). &lt;br class='manualbr' /&gt;FPGAs were newborns and were designed painfully with schematic and custom tools.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Synario&lt;/h2&gt;
&lt;p&gt;Synario was a milestone in the &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; industry, bringing affordable &lt;abbr title=&#034;Hardware Description Language. _ Some HDLs are : Verilog, SystemVerilog, VHDL, SystemC. _ First-generation (now obsolete) HDLs : Abel, CUPL etc&#034;&gt;HDL&lt;/abbr&gt; synthesis and simulation in an integrated framework, and offering Top-Down design, vendor-independence, portability, HDL simulation, generic schematics, etc&#8230; This was the beginning of our &#8220;crusade&#8221; to help these changes happen in the (French) industry.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;HDL FPGA Design Methodologies&lt;/h2&gt;
&lt;p&gt;At all times, the adoption of new Methodologies is a major challenge, and High Quality Training Courses with Expert Instructors were and still are the best way to facilitate the transition. It's therefore no surprise that we developed our own specific Training Course Material (Digital Design Basics, Abel, Verilog, and VHDL). &lt;br class='manualbr' /&gt;Synario users were the obvious target, but this Training activity quickly spread up with various partnerships (semi-houses, European Programs like Jessica) in France and in Switzerland : engineers loved our Training courses because of their concrete &amp; proven efficiency.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Services&lt;/h2&gt;
&lt;p&gt;In &#8216;97, with the turmoil in Design tools and EDA companies, we focused on &lt;em class=&#034;spip&#034;&gt;Services&lt;/em&gt; rather than products : Design sub-contracting, Consulting and indeed Training courses. The success was immediate and we designed more and more complex systems while the Programmable Logic chips went from a few thousands of gates to the (many) million(s) we use today. We were proud to demonstrate de-facto how well the methodologies we did teach worked for us.&lt;/p&gt;
&lt;p&gt;Since then, Synario and all its competitors (Viewlogic, Veribest&#8230;) disappeared (Synario was purchased by Xilinx), but the methodologies they introduced are now well established. The Synario nostalgics did find traces of it in the old Xilinx's ISE and Lattice ispLever.&lt;br class='manualbr' /&gt;Note that most of the concepts developed for Synario are now standard in all tools, more than 20 years later !&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;HDL Trainings Leader&lt;/h2&gt;
&lt;p&gt;The next logical step occurred at the end of &#8216;99 when ALSE became the official Doulos UK Partner to delivery the Doulos Training Course in France. Despite the success of ALSE's modest training course material, the decision was taken to switch to the extremely rich Doulos portfolio. The quality and the wide scope of the Doulos portfolio were key factors in the decision (VHDL , VHDL-AMS, Expert VHDL Design, Expert VHDL Verification, Verilog, &lt;abbr title=&#034;SystemVerilog (IEEE standard 1800) is an HDVL (Hardware Description &amp;#38; Verification Language). _ This is the Language that now supersedes both Verilog and VHDL, thus becoming the de facto Language of the next 20 years.&#034;&gt;SystemVerilog&lt;/abbr&gt;, &lt;abbr title=&#034;Property Specification Language. _ Normalis&#233; as IEEE 1850 and now part of VHDL-2008, thus language allows describing Properties and Assertions, thus enabling the ABV (Assertion Based Verification) methodology. _ A (roughly) equivalent to PSL can be found in SystemVerilog as &#8220;SVA&#8221;.&#034;&gt;PSL&lt;/abbr&gt;, SystemC, Expert SystemC, Tcl/Tk, etc). The Training courses are updated and improved with the continuous involvement of many engineers (including ALSE's). Our collaboration with Doulos is very tight.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Altera&lt;/h2&gt;
&lt;p&gt;In May 2003, ALSE became the &lt;strong&gt;Altera Technical Training Partner&lt;/strong&gt; in France.&lt;/p&gt;
&lt;p&gt;We built rapidly a new extensive and logical portfolio of Training courses for Altera with two major courses : one for Designing with Quartus II (3 days) and the other focused on Altera SOPC Nios II (3 to 5 days). Then, along the years and with the new devices, we added many other trainings.&lt;/p&gt;
&lt;p&gt;After the success we experienced in France, Altera asked us to offer these Training courses in other European countries and we currently serve Benelux, UK, Germany, The Netherlands&#8230; We built a cross-agreement with Doulos to take advantage of their international presence.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;&#8230; and today !&lt;/h2&gt;
&lt;p&gt;In 2024, after 24 years of continued growth and success, and after having developed so many IPs, ALSE is well established with customers from all over the world, with many facets :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Custom Design and Services,&lt;/li&gt;&lt;li&gt; Developing and selling innovative and High Performance IPs&lt;/li&gt;&lt;li&gt; Services in the Embedded Computing space&lt;/li&gt;&lt;li&gt; Delivering the FPGA Design and HDL Languages Training Courses in France&lt;/li&gt;&lt;li&gt; Designing and Delivering our FPGA Design trainings in France, Europe and North America&lt;/li&gt;&lt;li&gt; Delivering Embedded Linux trainings&lt;/li&gt;&lt;li&gt; Helping customers designing High Performance FPGA boards (even Agilex 7 boards)&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;All our Engineers are involved in the tasks above, and this is certainly contributing to our efficiency and to our credibility.&lt;/p&gt;&lt;/div&gt;
		
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		<title>Why ALSE ?</title>
		<link>https://www.alse-fr.com/Why-ALSE.html</link>
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		<dc:date>2016-09-06T13:17:17Z</dc:date>
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		<description>&lt;p&gt;It's Easy to work with ALSE !&lt;/p&gt;

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&lt;a href="https://www.alse-fr.com/-About-us-.html" rel="directory"&gt;About us&lt;/a&gt;


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 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;If you need help with your &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; project, you'll discover that ALSE can easily be the right company to work with&#8230;&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;p&gt;As &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; &amp; Embedded Systems Experts, we provide:&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Product Development&lt;/li&gt;&lt;li&gt; IPs&lt;/li&gt;&lt;li&gt; Consulting&lt;/li&gt;&lt;li&gt; Training Courses.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Our Charter:&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; Quality&lt;/li&gt;&lt;li&gt; On-Time delivery&lt;/li&gt;&lt;li&gt; Transparency &amp; Fairness&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;&lt;strong&gt;Quality&lt;/strong&gt;: Our work is guaranteed to meet or exceed your expectations, and it works first-time ! We have a long experience in the Design business and our customers enjoy our fast, efficient, clever, and dense architectures (one of our design did fit in a 5 times smaller device than the competition).&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;On-Time delivery&lt;/strong&gt;: We are (almost) nevr late ! We help you meet the most stringent deadlines. Even if you think it is hopeless, there is still a good chance that we could deliver the job on time&#8230;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Transparency &amp; Fairness&lt;/strong&gt;: We want Happy and FREE customers ! (see our Testimonials)&lt;br class='manualbr' /&gt;All our designs are delivered complete with all the documentation, and we transfer our know-how. We can also train you if necessary. So, once we have delivered and the system is tested, you will not need us to maintain or modify it !&lt;br class='manualbr' /&gt;Our business model is not based on captive and frustrated customers, but on successful projects and happy customers. And it works for us too: we prefer designing new projects (with high added value) than modify older designs.&lt;br class='manualbr' /&gt;&lt;em class=&#034;spip&#034;&gt;Transferring the complete know-how is a Win-Win situation&lt;/em&gt; and we enjoy the partnership-type relation we establish with our customers.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_ps'&gt;&lt;blockquote class=&#034;spip&#034;&gt;
&lt;p&gt;Do you know it usually takes us&lt;br class='manualbr' /&gt;no more than 2 to 3 weeks&lt;br class='manualbr' /&gt;to design a complex &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; ?&lt;/p&gt;
&lt;/blockquote&gt;
&lt;p&gt;With ALSE, Your Success is Guaranteed !&lt;/p&gt;&lt;/div&gt;
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		<title>Testimonials</title>
		<link>https://www.alse-fr.com/Customer-Testimonials.html</link>
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		<dc:date>2016-09-06T13:11:20Z</dc:date>
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		<dc:subject>Livre d'Or</dc:subject>

		<description>
&lt;p&gt;Disclaimer: these articles are expressing the authors own opinions. The statements are not necessarily endorsed by their company or employer.&lt;/p&gt;


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&lt;a href="https://www.alse-fr.com/+-Livre-d-Or-+.html" rel="tag"&gt;Livre d'Or&lt;/a&gt;

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 <content:encoded>&lt;div class='rss_chapo'&gt;&lt;p&gt;Disclaimer: these articles are expressing the authors own opinions. The statements are not necessarily endorsed by their company or employer.&lt;/p&gt;&lt;/div&gt;
		
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