A.L.S.E the FPGA Experts

NUMERIC_STD Issues.

2017-03-01T13:28:56Z

Description

The IEEE numeric_std library issued (eg) in Nov 1994, and which (as of 2022) is still used in the latest versions of the Simulation and Synthesis tools, implements incorrectly the multiplications of signed/unsigned vectors by an integer. Moreover, the resize function it includes can produce incorrect results without warning.

Fixing these functions is not difficult but my attempts to have the VHDL working group fix this library have been unsuccessful. As a consequence, you should understand and take into account these “features”. This is the purpose of this page.

Multiplication issue : Functions affected

Here are the original prototypes (in IEEE.numeric_std) :

 -- Id: A.17 function "*" ( L: UNSIGNED; R: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED((L'length+L'length-1) downto 0). -- Result: Multiplies an UNSIGNED vector, L, with a non-negative -- INTEGER, R. R is converted to an UNSIGNED vector of -- SIZE L'length before multiplication. -- Id: A.18 function "*" ( L: NATURAL; R: UNSIGNED) return UNSIGNED; -- Result subtype: UNSIGNED((R'length+R'length-1) downto 0). -- Result: Multiplies an UNSIGNED vector, R, with a non-negative -- INTEGER, L. L is converted to an UNSIGNED vector of -- SIZE R'length before multiplication. -- Id: A.19 function "*" ( L: SIGNED; R: INTEGER) return SIGNED; -- Result subtype: SIGNED((L'length+L'length-1) downto 0) -- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is -- converted to a SIGNED vector of SIZE L'length before -- multiplication. -- Id: A.20 function "*" ( L: INTEGER; R: SIGNED) return SIGNED; -- Result subtype: SIGNED((R'length+R'length-1) downto 0) -- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is -- converted to a SIGNED vector of SIZE R'length before -- multiplication.

Multiplication Issue

As we can see above (in the comments), when multiplying a vector by an integer, the integer is converted into a vector of the same width as the other operand !!!

As a consequence, the result's width is forced to two times the width of the signed/unsigned vector, just as if the vector was squared (multiplied by itself), which absolutely does NOT make sense.

The result is either too short or too large.

Consequences

Multiplying a vector by 1 (or a small integer) creates a vector twice as large.
Quite inefficient, a bit ridiculous, but relatively harmless.
Multiplying a 128-bits vector by 7 (eg) creates a 256-bits results.
Same remark as above.
The result of Multiplying an 8-bits unsigned vector by 256 is a 16-bits vector (okay by chance) but with a value of ZERO ! See the test case included.
This is definitely VERY WRONG :-( and the multiplication result is not usable.
Multiplying a 8-bits signed vector by 1000 (decimal) produces an incorrect result (actually V * 232) and the result is limited to 16 bits anyway.
This is also very wrong.

Note that simulators will typically issue truncation warnings during the simulation (run-time) in the most offending cases, or refuse to compile if the result width is not what the user believed (which is how I uncovered the issue).
But Synthesis tools will compile and generate hardware which can potentially produce incorrect results, and this is not acceptable.

Are these functions useful ?

Certainly. They are required by the principle of numeric_std which is to extend arithmetic operators to vectors that represent numbers (signed and unsigned).

Moreover, Synthesis tools are usually relatively smart when they see multiplications by constants, in which case they know how to replace the multiplication by adder(s).

However, their use has been limited (which explains why the incorrect implementation hasn't been reported heavily before). One can note that the older Synopsys library “std_logic_arith” did not provide the multiplication of signed/unsigned vector by integers, and therefore could not have the same problem.

Repairing NUMERIC_STD ?

Fixing the affected functions is not complicated : it suffices to convert the natural or integer into a 32-bits vector ! The resulting width at least starts making some sense (=Operand width + 32) and no truncation / incorrect result can occur. If the result is still too large for you (like when you multiply by an integer range), you just have to resize the result. If you lose information in the resize (you resized into a too short vector), YOU WILL NOT GET A WARNING.

BUT, the issue is that numeric_std will probably never be fixed !

So you have to take care of your code and make sure you are not affected by the library errors, as explained below.

Conclusion

In spite of the library clumsiness (shift operators, resize issue, and this bug in particular), I still keep recommending using numeric_std instead of other non-IEEE libraries.

My VHDL Coding Style Guide is updated :

Do not multiply signed/unsigned vectors by Integers.
- Use slices and adders if you multiply by an integer constant
- Convert the integer in a properly sized signed or unsigned vector before multiplying.
- Keep in mind that if resize creates an incorrect value due to truncation, you will NOT be warned !

and the older recommendation remains :

Avoid using shift/rotate operators from numeric_std (use slices & concatenation)

And finally : kudos to the brilliant Technical Support at Mentor / Model Technology !

Utilities

2016-09-20T21:44:56Z

© 2009 ALSE. All rights reserved. NOTICE OF DISCLAIMER about Free IPs and other information on the ALSE Web site. ALSE is providing design, code, or information “as is.” By providing the design, code, or information ALSE makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. You are entirely responsible with any use you make of the provided information, code or design. ALSE expressly disclaims any warranty whatsoever with respect to the adequacy of the information, or to the suitability to any use beyond education, including but not limited to any warranties or representations that this information is free from claims of infringement and any implied warranties of merchandability or fitness for a particular purpose.

These utilities are free to use, with the usual disclaimer above: use this at your own risk.

SystemVerilog definition files for Crimson Editor.
unzip into Crimson's base installation directory.

Verilog RTL ROM Generator
This Tcl/Tk utility reads in a memory contents file in Intel-Hex format and produces synthesizable Verilog code for the ROM.

VHDL Quick Reference sheet.
Standard RTL & Test bench templates and Numeric_std reminder, all in one sheet.

Numeric_std cheat sheet.

CPU_Time.
Utility (Tcl) to capture the current Date & Time information (“wall clock time”) from within a VHDL simulation. (c) ALSE, for use with ModelSim. Your batch simulation can record start and end time in the VHDL output. Great also for simulation run-time optimization.

VHDL templates

2016-09-20T21:38:13Z

If you are looking for well-written code to analyze, or coding examples, please check also our Free IP section where you can find the source code of many IPs, which are reasonably simple to understand while implementing all the concepts needed for designing complex functions.

We have dedicated this page to Code Templates, so beginners or more advanced designers can simply cut & paste from the snippets. There is enough code here to be used in 90% of VHDL code (both RTL and Simulation).

Beginners: don't miss some Application Notes especially “Writing Test benches”.

Note : the code below is compatible with all (decent) synthesis tools (it does not use VHDL 2008 constructs).

RTL Libraries

Library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;

Simulation Libraries

 use STD.TEXTIO.all; Library IEEE; use IEEE.std_logic_TEXTIO.all; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;

Resynchronization Flip-Flop

Ar <= A when rising_edge(Clk);

Synchronous Process Template

process (Rst,Clk) -- NOTHING ELSE in the sensitivity list ! -- variables (if any) go here begin if Rst='1' then -- EVERY signal assigned below must be reset here ! <<>> elsif rising_edge(Clk) then <<< Your code goes here (only) >>> end if; end process;

Tri-state output

Qtri <= Dout when OE='1' else 'Z';

Multiplexer

Q <= A0 when Sel='0' else A1;

Direct Instantiation

Don't use “components” !

QUAD_inst: {{Entity work.}}QUAD(RTL) port map ( Rst => Rst, Clk => Clk, A => Ar, B => Br, Cnt => Position, Dir => open );

Cannot read outputs

We assume you don't use VHDL 2008 (for reasons found in our Coding Style Guide), so you will not be able to read an output signal.

The workaround is to declare and work on an internal signal which can be of a different type as below.

 signal iCount : unsigned(Count'range); -- unsigned better than SLV internally Begin -- architecture Count <= std_logic_vector(iCount); -- SLV required at the interface (ports)

7-Segments decimal Decoder

process(Data) begin Seg <= (others => '-'); -- optimize for A..F with don't care case Data is when x"0" => Seg <= "1111110"; when x"1" => Seg <= "0110000"; when x"2" => Seg <= "1101101"; when x"3" => Seg <= "1111001"; when x"4" => Seg <= "0110011"; when x"5" => Seg <= "1011011"; when x"6" => Seg <= "1011111"; when x"7" => Seg <= "1110000"; when x"8" => Seg <= "1111111"; when x"9" => Seg <= "1111011"; when others => null; -- required to cover the 6551 remaining cases end case; end process;

Demux / binary to one-hot

Process (i) begin MyVect <= (others=>'0'); MyVect(i) <= '1'; -- i is an integer (range) end process;

Optimal One-Hot to Binary

In VHDL, this represents a quite challenging problem if you want to infer an efficient hardware implementation.
In Verilog, the use of a synthesis pragma was common.
In SystemVerilog, the unique case statement is the answer.

If you are not too concerned by the amount of logic generated, you can use an intuitive solution (a case statement). The optimal solution is below.

-- OneHotDecoder.vhd -- ---------------------------------------------------- -- Optimal One-Hot to Binary Decoder -- ---------------------------------------------------- -- (c) ALSE / Bertrand CUZEAU - FPGA.fr -- Library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- --------------------------- Entity OneHotDecoder is -- --------------------------- port( Din : in std_logic_vector(7 downto 0); Dout : out std_logic_vector(2 downto 0) ); End entity OneHotDecoder; -- -------------------------------------- Architecture RTL of OneHotDecoder is -- -------------------------------------- Begin process (Din) variable R : unsigned (Dout'range); begin R := (others=>'0'); for i in Din'range loop if Din(i)='1' then R := R or to_unsigned(i,R'length); end if; end loop; Dout <= std_logic_vector(R); end process; End architecture RTL;

Butterfly (bus order swap)

-- Note that both vectors start/end at index 0 Process (MyVect) begin for i in MyVect'range loop SwappedVect(i) <= MyVect(MyVect'high-i); end loop; end process;

Power On Reset (POR)

When there is no (reliable) external reset input, it is very recommended to generate a global and general Reset of the entire FPGA at start up. This is the function of the simple module below. The “magic vector” 1010 (decimal value 10) is too small in cases of FPGA families in which Flip-Flops come up in an indetermined state (like several Actel families). It is however suitable for SRam FPGAs.

The Reset output will have to be resynchronized to all the different clock domains, but it's another story…

-- ------------------------------------ -- Power On Reset with NO reset input -- ------------------------------------ -- Author : Bert Cuzeau - ALSE -- 10 clock cycles reset pulse issued at start up -- Suitable for SRam FPGAs Library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- ---------------------------------------- Entity POR is -- ---------------------------------------- Port ( Clock : in std_logic; -- clock input Reset : out std_logic ); -- reset output end entity POR; -- ---------------------------------------- Architecture RTL of POR is -- ---------------------------------------- signal Cnt : unsigned (3 downto 0) := (others=>'0'); -- init for simulation signal iRst_n : std_logic := '0'; -- init for simulation Begin Reset <= not iRst_n; process (Clock) begin if rising_edge(Clock) then if Cnt /= 10 then -- If counter hasn't reached this value then Cnt <= Cnt + 1; -- keep counting iRst_n <= '0'; -- and force the Reset else iRst_n <= '1'; -- release the Reset end if; end if; end process; end architecture RTL;

Synchronous Edge Detector

Synchronous Edge Detector

The input D signal can be asynchronous.

-- ------------------------------------------ Architecture RTL of EdgeDet is -- ------------------------------------------ signal Dr, Drr : std_logic; Begin Dr <= D when rising_edge(Clk); Drr <= Dr when rising_edge(Clk); Rose <= Dr and not Drr; Fell <= Drr and not Dr; Changed <= Dr xor Drr; end architecture RTL;

Simple Memory Inference

Please refer to ALSE training course.

-- RTL (synthesizable) Synchronous Single Port Memory -- ---------------------------------------------------------- -- (c) ALSE - http://www.alse-fr.com -- Author : Bert Cuzeau -- Contact : info@alse-fr.com -- Note : Uses unconstrained arrays in port Library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- ------------------------------------------ Entity RamTest is -- ------------------------------------------ port ( Clk : in std_logic; Din : in std_logic_vector; Dout : out std_logic_vector; WE : in std_logic; RdAddr : in std_logic_vector; WrAddr : in std_logic_vector ); end RamTest; -- ------------------------------------------ Architecture RTL of RamTest is -- ------------------------------------------ subtype Data_t is std_logic_vector (Dout'range); type Mem_t is array (0 to 2**RdAddr'length-1) of Data_t; signal Mem : Mem_t; Begin process (Clk) begin if rising_edge(Clk) then Dout <= Mem (to_integer(unsigned(RdAddr))); -- Synchronous Read if (WE = '1') then Mem (to_integer(unsigned(WrAddr))) <= Din; end if; end if; end process; end architecture RTL;

Inference vs Instantiation is an important topic which is explained in our Training courses. The code above is normally suitable to all synthesis tools and FPGAs (that embark embedded memory blocks).

While it is possible to infer true Dual-Port memories with modern synthesis tools, instantiation is usually more recommended.

Simple RTL assertions

assert not (rising_edge(Clk) and FifoWR='1' and Fifo_Full='1') report "Fifo Write Violation !!!" severity failure;

Note : it is not a PSL assertion, it shows how to take advantage of the VHDL “assert” statement and it does not require any specific simulator or feature.
PSL Assertions are more versatile and powerful (especially for their temporal layer).