A.L.S.E the FPGA Experts

HyperRam Memory Controller

2017-11-28T07:29:40Z

The HyperRAM memories, based on low-power PSRAM technology and using the recent HyperBus interface, are a very welcome addition to the traditional RAM memories portfolio : they have been optimized for Mobile and Automotive applications and are an excellent fit for many projects.

They provide good Bandwidth performance
The interface, known as “HyperBus”, offers a low signal count (Address, Command and Data using only eight DQ pins)
They offer Low Power consumption
Typical power consumption during burst read is about 60 mA only.
Efficient protocol, with Hidden Refresh mode, and various burst modes.
Most devices are available for Automotive Temperature range…

But… by the experience of many users, these memories are actually surprisingly complex to use reliably and efficiently with most existing controllers.

ALSE has designed an extremely efficient and versatile HyperRam Memory Controller providing high performance (up to 333 MBytes/s, which is 1.5 x times faster than a 16 bits PSRAM running at 108 MHz).
It is also extremely reliable while being compact. Our customers have compared and reported our controller as a clear winner.

Main Technical Features

High-Performance HyperRam Controller supporting Burst Mode for Read/Write transfers, to get optimized bandwidth and minimal switch fabric overhead.
Memory Operating Frequency typically up to 166 MHz or more, depending on FPGA and Memory speed grades, and (more marginally) on the customer PCB. This delivers a bandwidth up to 333 MBytes/s or more, with only 12 x IO pins (CS, Clk/Clk_n, DQS, DQ[7:0])
16 bits Slave Data Interface with Burst (and wrap) support. Typically, the Controller will serve a Master that can be a Nios II, Nios V, RiscV, Xilinx MicroBlaze, or another CPU, with or without caches, with or without Bursting.
Other hardware masters (like DMA engines) are of course also possible (e.g : Video streaming DMAs, Scatter-Gather DMAs, Frame buffers etc…)
16 bits Slave Register Interface to access HyperRAM memory registers (for configuring Output Drive Strength, Burst Wrap, etc…)
Burst Wrap mode support (for efficient transfer with caches).
Very low FPGA resource usage (Logic Cells and Memory Blocks)
Versatile : this IP can be used in most existing FPGA devices that have internal memory blocks.
Intel Platform Designer compliant, with an advanced configuration panel.
Highly configurable. A lot of options and settings are available to parameterize and optimize the controller.
Provided with sophisticated SDC Timing Constraints.
Comes with advanced Hardware Tester Reference Designs in source code. Allows to test and qualify custom boards . The testers are ready to use for several FPGA Design Kits :
Tested on the Xilinx Artix7 Trenz TE0725 kit
Tested on the Cyclone 10 LP FPGA Evaluation Kit
Transparent supports for dual-die HyperRam chips !
AXI4 support for Xilinx

Typical waveforms

Here is above a typical waveform of a Write access, with initial Latency.

hyper write

Here is above a typical waveform of a Read accesses, with initial Latency.

hyper read

Examples of supported Memories

ISSI IS66/67WVH8M8ALL/BLL - 64Mb
Cypress S27KL/S0641 - 64Mb
Cypress S70KL/S1281 - 128Mb
etc …

Synchronous SRAM (SSRAM) Controller

2016-11-07T14:28:21Z

Low Latency is often very important in many fields such as cache-based products, broadcast, networking and communications applications, video streaming / video games, etc …
Synchronous SRAM memories are very good candidates for such latency-sensitive applications, thanks to their (very) low latency (typically one clock cycle), high performance.
Interfacing such memories to an FPGA is easy using the optimized ALSE controller. Thanks to its very small FPGA footprint and low resource usage, this controller fits in the smallest FPGAs, which makes it also perfect for the Automotive and Consumer Markets.

Main Technical Features

High-Performance Controller supporting Burst Mode for Read/Write transfers, to get optimized transfer speed and minimal switch fabric overhead.
Memory Operating Frequency typically up to 133 MHz, depending on FPGA and Memory speed grades, and (more marginally) on the customer PCB characteristics.
32bits Slave Interface (Avalon-MM based) with Burst support. Typically, the Controller will serve a Master that can be an Altera Nios II CPU (32bits), with or without caches, with or without Burst mode. A hardware master (DMA) is of course also possible (e.g : Video streaming DMAs, etc …)
Specific version of the controller for No Bus Latency memories, also called Zero Wait States memories (such as ISSI IS61NLF204836B / IS61NLF409618B, or Cypress CY7C1471BV33 / CY7C1473BV33), for 100% bandwidth utilization (no dead cycles)
Very low FPGA resource usage : less than 200 Logic Cells, and two memory blocks
Versatile : This IP can be used in all FPGA devices (Intel / Altera, Xilinx, Lattice, MicroSemi / Actel) having internal memory blocks.
Provided with sophisticated SDC Timing Constraints, Hardware Tester Reference Designs, etc…

Typical waveforms

SSRAM no bus latency waveform

Here is above a typical waveform of consecutive Read/Write accesses, with/without bursts, with Zero Wait state (no bus latency) and thus 100% bandwidth utilization. The clock can be up to 133 MHz here.

Examples of supported Memories

ISSI IS61LPS25632B
ISSI IS61NLF204836B/IS61NLF409618B
Cypress CY7C1471BV33 / CY7C1473BV33
etc …

Quad SPI Controller

2016-09-27T15:06:28Z

For an FPGA-based project, replacing bulky, pin-consuming, and complex Parallel Flash Memories by modern Quad-SPI Flash devices is very exciting in many respects.
It drastically reduces the FPGA pin count and thus enables smaller (and cheaper) packages. It also reduces the power consumption, minimizes the PCB area & complexity, reduces the BOM, while providing good transfer speed, etc…

The major issue against Quad SPI memories is that Parallel Flash Memories are usually much simpler to interface with, and may even not require any specific controller (though this is less and less true).

At A.L.S.E, we have taken into account this growing demand and we have developed an extremely efficient and compact (yet affordable) Quad-SPI Controller, which has already been adopted by many customers, especially in the very demanding and competitive field of Automotive Equipment Manufacturers.

Main Technical Features

High-Performance Controller !
In some applications, we have seen boot time reduction by a factor of more than 20x !
Supports Burst Mode transfers for optimized transfer speed and minimal switch fabric overhead.
Takes fully advantage of the multi-lanes (x4) capability.
Transfer speed up to 52MBytes/s (Quad SPI clock up to 104 MHz) or more, depending on FPGA and QSPI Memory type and speed grades.
Quad IO Programming (x4) is also supported

Versatile

This IP can be used in all FPGA Altera devices (including MAX / MAXII families, since no memory blocks are needed in some configurations). For other FPGA vendors (Xilinx, Lattice, MicroSemi/Actel), please contact ALSE.
We support most Flash Vendors & types (Winbond, Spansion, Numonyx, Micron…).
Support the latest densities, like 256MBits/512MBits/1Gbits (4 bytes-address mode)
Includes Clock Domain Crossing Management for best area and transfer speed results.
Special “Direct Command Mode” available to access Quad SPI low-levels commands directly from the Avalon Master interface, allowing memory specific operations as Lock/Unlock, Read of Status Registers, Flash ID, Software Reset, etc …
Support of the additional QSPI Hardware Reset pin for Flash supporting it
Multi-chip management. An option allows to parallel two QSPI Flash devices (with an extra CS signal) to double the storage space. Ask ALSE for this.
Modular: Embedded programming can be activated or deactivated, for security reason or for area minimization purpose. FIFO depths can be easily adapted regarding customer FPGA constraints.

Simple Interface

32bits Slave Interface (Avalon-MM) with Burst support.
Typically, the Controller will serve a Master that can be an Altera Nios II CPU (32bits), with or without Caches, with or without Burst mode.

A hardware master is of course also possible so this controller can also be used without an embedded processor.

Compact !

The area can be trimmed down to less than 600-700 Logic Elements, and even 0 (zero) internal memory block.
Partial Transparent CFI Flash Emulation (a very special feature developed by ALSE), designed and optimized to be compliant with Altera nios2-flash-programmer. This option greatly facilitates the adoption of the Quad-SPI as a replacement of standard CFI Parallel Flash memories (programming is essentially the same as for Parallel Flash devices).
Easy integration in Altera Qsys or manually (no processor in system)
Delivered with sophisticated SDC Timing Constraints, and Hardware/Software Reference Designs, etc…

Device Support

Examples of supported Quad-SPI Memories :

Spansion / Cypress S25FL129P, S25FL512, etc …
Micron M25Q256 etc…
Macronix 25L256 etc…
Winbond W25Q80, W25Q16, W25Q32, etc …
Numonyx N25Q256, N25Q512, etc …
etc …

Even if your specific Flash is not supported (to be verified), ALSE could easily add it to the list.

NAND Flash Controller

2016-09-27T14:49:51Z

NAND Flash memories are attractive due to their very high density and low price.
However, when compared to NOR Flash Memories, they are challenging because they are not fault-free (they need ECC Correction, Bad Block management, etc …) and they are organized like disk drives, with atomic transfers being a whole “page” (no random read/write with data integrity).
As a consequence, they cannot be used as straight replacement for NOR Flash memories : they require a specific Controller.

At A.L.S.E, we have applied our very strong experience in Memory Controllers to take into account this growing demand and we have developed an extremely compact and efficient -yet low-cost- ONFI SLC NAND Flash Memory Controller with Error Check and Correct.

In spite of the compact size, the transfer performance achieved is extremely high (thanks to the embedded and autonomous DMA engine). However, this IP remains simple to use, thanks to its standard Interfaces and its Automatic and Transparent ECC scheme (based on BCH algorithm).

Main Technical Features

High-Performance Controller
Supports NAND Flash Asynchronous Timing Mode from 0 (slowest) to 5 (fastest).
Supports 2KB, or 4KB or 8KB NAND page size, and latest (at time of writing) NAND memory densities : 32Gbits, 64Gbits, 128Gbits, etc…
Supports 4 bytes or 5 bytes NAND Address Command.
Support of multiple Dies (CE#) Flash memories.
Ability to control the NAND Flash with or without the use of the RDY/BUSY NAND Flash pin.

Easy Interfaces

32bits Bi-directional Embedded DMA Engine (Avalon-MM) from/to User Logic, with Burst Mode support for optimized transfer speed and minimal switch fabric overhead, and Interrupts generation at end of operation (Erase/Program/Read) to minimize CPU overhead.
32 bits Registers Slave Interface (Avalon-MM) for Control.
Typically, the Controller will serve a Master that can be for example an Altera Nios II CPU, an ARM-A9 HPS, another embedded CPU, or no CPU at all (processor-less applications, full hardware solution).
Ability to read the NAND Status Register for high-level Bad Block detection and Management, and status of any other operation.

Error Check & Correct

Automatic & Transparent Error Check and Correct. The ECC is based on BCH algorithm, 8 bits correction for 540 bytes of Data).
Please contact ALSE for other ECC schemes. Simpler ECC Hamming code (1 bit correction) is also available, for smaller FPGA resource usage.
Additional data checking using 32-bits CRC for even better performance and smaller read latency.

Versatile

This IP can be used in all FPGA devices (Altera, Xilinx, Lattice, Actel/MicroSemi). However, internal memory blocks must be available, so CPLDs like Altera MaxII & MaxV are not supported.

Can be integrated seamlessly using Altera Qsys tool, or manually. It is maintained up-to-date with the latest version of the FPGA tools (older versions on request).
Compact. With ECC BCH enabled (8bits correction), the area is typically around 4,000 Logic Elements, and 10 to 20 memory blocks (M9K) are used (depending the NAND Page Size). With ECC Hamming (1bit correction) enabled, the area is typically less than 1,500 Logic Elements, and 4 to 10 memory blocks are used.
Provided with sophisticated SDC Timing Constraints, for easy IP integration.
Provided with a Hardware or Software Reference Design, an example API, etc… ALSE can optionally test the controller on your custom FPGA board before delivering the IP.
First-class English/French Technical Support (E-mail and Telephone, extended CET hours).

Device Support

Example of NAND Flash Memories supported :

Micron MT29F4G08ABADAWP_nand
Micron MT29F32G08ABAAAWP
Micron MT29F128G08AJAAAWP

Please contact ALSE for other NAND Flash models.

The ALSE NAND Flash Controller is the perfect compact and yet very efficient solution to attach a NAND Flash memory from your FPGA.
Don't hesitate to contact us for any questions about this IP.

PSRAM Controller

2016-09-27T13:22:43Z

Power consumption is more and more critical in many applications, such as battery-powered equipments, very low power applications and other fields like automotive, military, etc … Thus, choosing and using a very low power external memory such as a PSRAM (Pseudo-Static RAM) memory can be a very interesting solution (less than 40 mA during burst read operations @ 104 MHz) ALSE has developed a very compact and efficient controller that can be easily integrated in any FPGA project.

Main Technical Features

High-Performance Controller supporting Burst Mode for Read/Write transfers, to get optimized transfer speed and minimal switch fabric overhead.
Memory Operating Frequency > 100 MHz, depending on FPGA and Memory speed grades, and (more marginally) on the customer PCB characteristics.
32bits Slave Interface (Avalon-MM based) with Burst support.
Typically, the Controller will serve a Master that can be an Altera Nios II CPU (32bits), with or without caches, with or without Burst mode.
A hardware master (DMA) is of course also possible.
Support of different PSRAM memory standards (e.g : Micron CellularRam 1.0/1.5/2.0)
Support of PSRAM memory with Multiplexed address/data bus
Versatile.
This IP can be used in all FPGA devices (Intel / Altera, Xilinx, Lattice, MicroSemi / Actel) having internal memory blocks.
Easy integration using Altera Qsys, or manually.
Provided with sophisticated SDC Timing Constraints, Hardware Tester Reference Designs, etc…

Examples of supported Memories

Micron MT45W2MW16BGB
Micron MT45W4MW16BCGB
ISSI 66WVD4M16ALL
etc …

If your specific Flash is not supported yet, ALSE can easily add its support to this list.

SRAM Controller

2016-09-27T13:02:41Z

A.L.S.E has developed a very compact and efficient Static RAM controller that can be easily integrated in any FPGA project.

Main Technical Features

High-Performance Controller supporting Burst Mode for Read/Write transfers, to get optimized transfer speed and minimal switch fabric overhead.
Asynchronous interface management with fastest Memory timings, depending FPGA and Memory speed grades, and Customer board Timing Constraints.
16/32bits Slave Interface (Avalon-MM based) with Burst support. Typically, the Controller will serve a Master that can be an Altera Nios II CPU (32bits), with or without Caches, with or without Burst mode. A hardware master (DMA) is of course also possible.
Generic for different SRAM memory densities (address bus) and data bus size
Versatile. This IP can be used in all FPGA devices (Altera, Xilinx, Lattice, MicroSemi Actel) having internal memory blocks (CPLDs not supported).
Easy integration in Altera Qsys or manually (non-SOPC designs).
Comes with sophisticated SDC Timing Constraints, and Hardware Tester Reference Design.

This controller replaces the tri-state bridge. It provides high performance enhancement, as well as a reliable interface (checked and optimized with SDC constraints).