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	<title>A.L.S.E the FPGA Experts</title>
	<link>https://www.alse-fr.com/</link>
	<description>A.L.S.E: Advanced Logic Synthesis for Electronics, offers a complete range of Services, IPs, Training courses and Boards to help you with the design of FPGA-based and EmbeddedSystems.</description>
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		<title>PowerLink</title>
		<link>https://www.alse-fr.com/PowerLink.html</link>
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		<dc:date>2016-11-08T06:34:56Z</dc:date>
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		<description>&lt;p&gt;POWERLINK is our choice as of Standard Real-time Industrial Ethernet Network. We have acquired a serious know-how and we have the capability to quickly port this network to any &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt;, as we have done for the Altera Max10 when it became available.&lt;/p&gt;

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&lt;a href="https://www.alse-fr.com/-Industrial-Ethernet-.html" rel="directory"&gt;Industrial Ethernet&lt;/a&gt;


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 <content:encoded>&lt;div class='rss_texte'&gt;&lt;h2 class=&#034;spip&#034;&gt;Introduction&lt;/h2&gt;
&lt;p&gt;After accumulating some experience with other Industrial Networks on &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt;, we converged on retaining only &lt;a href=&#034;https://www.ethernet-powerlink.org/&#034; class=&#034;spip_out&#034; rel=&#034;external&#034;&gt;POWERLINK&lt;/a&gt; as well as our own Ultra-Low Latency Gigabit ring.&lt;/p&gt;
&lt;p&gt;POWERLINK is a fast real-time field bus based on standard Ethernet. &lt;a href=&#034;http://openpowerlink.sourceforge.net/web/&#034; class=&#034;spip_out&#034; rel=&#034;external&#034;&gt;openPOWERLINK&lt;/a&gt; is an open-source implementation of this protocol, and comes with example designs targeting Intel (previously Altera) FPGAs.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Experience&lt;/h2&gt;
&lt;p&gt;Our experience with POWERLINK was very successful :&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; We quickly mastered the POWERLINK Slave Development Kit&lt;/li&gt;&lt;li&gt; We were able to build fully working slaves on very low cost FPGA boards (including the $25 BeMicroMax10 !)&lt;/li&gt;&lt;li&gt; The interaction with the openPOWERLINK maintainers was easy and productive.&lt;/li&gt;&lt;li&gt; B&amp;R offers a serious support for Powerlink adopters.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Take a look at &lt;a href='https://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/openpowerlink_max10.pdf' class=&#034;spip_in&#034; title=&#034;this presentation &#8211; PDF (1.1 MiB)&#034; type='application/pdf'&gt;this presentation&lt;/a&gt; to find out more details about the systems we implemented.&lt;/p&gt;&lt;/div&gt;
		
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		<title>Ultra Low Latency Network</title>
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		<dc:date>2016-10-04T17:24:21Z</dc:date>
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		<dc:language>en</dc:language>
		
		



		<description>&lt;p&gt;No existing Industrial Network provided the performance (latency &amp; throughput) that a customer application required, so we have developed this Ultra-Low Latency redundant network.&lt;/p&gt;

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&lt;a href="https://www.alse-fr.com/-Industrial-Ethernet-.html" rel="directory"&gt;Industrial Ethernet&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_texte'&gt;&lt;h2 class=&#034;spip&#034;&gt;Introduction&lt;/h2&gt;
&lt;p&gt;Gigabit Ethernet over copper twisted pairs (1000BASE-T) is an ubiquitous, easy,
and extremely reliable Physical Medium.&lt;br class='manualbr' /&gt;ALSE has developed a lot of experience around this technology, like the very
innovative &lt;abbr title=&#034;Gigabit Ethernet Data Exchange Kit. &#8220;Hardware Stack&#8221; Concept invented by ALSE, GEDEK is a processor-less autonomous block which implements the Ethernet protocols required to establish, maintain, and perform high performance data exchange over standard Ethernet.&#034;&gt;GEDEK&lt;/abbr&gt; communication kit (processor-less hardware stack) and allowed
achieving reliably unprecedented data throughput. This technology has been used
in hundreds of systems all over the world.&lt;/p&gt;
&lt;p&gt;One of our clients expressed the need to build an architecture with up to more
than 20 regulation and control boards interconnected together, and with a
requirement that all boards should be updated with the regulation data
from ALL OTHER boards during the first half of a single PWM cycle
(targeted at 20 kHz).
In other words, all the boards should see all the other board's data in no more
than 25 micro-seconds.&lt;/p&gt;
&lt;p&gt;Another requirement was the ability to implement &lt;em class=&#034;spip&#034;&gt;redundancy&lt;/em&gt;.&lt;/p&gt;
&lt;p&gt;Quite naturally &lt;strong&gt;Gigabit Ethernet&lt;/strong&gt; comes to mind to implement the inter-boards communication.&lt;br class='manualbr' /&gt;However, even under underestimated conditions (20 slaves, 20 kHz, no redundancy),
40 Ethernet frames must circulate in much less than 25 &#181;s.
This simple calculation shows that a standard (store-forward) architecture,
even with a near zero delay (like GEDEK) would be outperformed by a ratio greater
than four !&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Are existing solutions available ?&lt;/h2&gt;
&lt;p&gt;We conducted a careful pre-study and reached the conclusion that NO SOLUTION existed
in the market that reached only a fraction of the performance required !&lt;/p&gt;
&lt;p&gt;The table below, extracted from a very &lt;a href=&#034;https://www.ethernet-powerlink.org/fileadmin/user_upload/Dokumente/Dokumente/EPSG_IEF2ndEdition_en_WEB.pdf&#034; class=&#034;spip_out&#034; rel=&#034;external&#034;&gt;interesting article&lt;/a&gt; about Industrial Ethernet shows the state of the art.&lt;/p&gt;
&lt;p&gt;[table]&lt;/p&gt;
&lt;div class='spip_document_37 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;42&#034; data-legende-lenx=&#034;x&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;img src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L474xH310/indnetwcycletime-e5817.jpg?1782755388' width='474' height='310' alt='' /&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-37 '&gt;&lt;strong&gt;Industrial Ethernet standards Cycle Time
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;&lt;h2 class=&#034;spip&#034;&gt;Our solution&lt;/h2&gt;&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; We use completely &lt;strong&gt;standard IEEE 802.3-2008 Ethernet frames&lt;/strong&gt;.&lt;/li&gt;&lt;/ul&gt;&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; We implement a &lt;strong&gt;&#8220;circular&#8221; bi-directional (dual) ring&lt;/strong&gt;.
Two frames circulate in opposite directions for a full turn, thus already
implementing a first redundancy.&lt;/li&gt;&lt;/ul&gt;&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; We use the &lt;strong&gt;Cut-Through Forwarding&lt;/strong&gt; technology in our own optimized switch
to reach an absolute minimal latency.&lt;/li&gt;&lt;/ul&gt;&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; We use the &lt;strong&gt;Summation Frame&lt;/strong&gt; method
(each node adds it's own data in a slot of the circulating frame).&lt;/li&gt;&lt;/ul&gt;&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; We use a &lt;strong&gt;fully Hardware implementation&lt;/strong&gt;, thus removing any software interaction
or limitation to the performance. In Hardware, decisions can be taken in less
than 10 nanoseconds (ie practically at each incoming byte in the GbE link),
with no jitter.&lt;/li&gt;&lt;/ul&gt;&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; We re-used (and customized) our optimized and well proven Gigabit-only &lt;abbr title=&#034;Media Access Controller. The Ethernet (802.3) MAC block is connected to the Media Interface of the Ethernet PHY (the PHYsical transceiver chip) in order to send and receive streams of bytes.&#034;&gt;MAC&lt;/abbr&gt;
(Media Access Control).&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Note : We have implemented several clever optimizations to further reduce our cut-through
switch latency. The details are only available after signing an NDA.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Network Topology&lt;/h2&gt;
&lt;p&gt;The figure below shows 9 boards connected together, one of which being the Master.&lt;/p&gt;
&lt;div class='spip_document_39 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;25&#034; data-legende-lenx=&#034;&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;img src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH554/netw_topo-b6029.jpg?1782755774' width='500' height='554' alt='' /&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-39 '&gt;&lt;strong&gt;Network (ring) Topology
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;&lt;h2 class=&#034;spip&#034;&gt;Test System&lt;/h2&gt;
&lt;p&gt;We have used 9 DE2-115 &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; kits attached together mechanically to form a &#8220;tower&#8221;.
See picture below. The DE2-115 (used in some Training courses) was available and it comes with two GBE interfaces (Marvell 88E1111 &lt;abbr title=&#034;PHYsical Interface. Device in charge of handling (encoding and decoding) the lowest layer of the protocol (the physical signals). In case of Ethernet, the PHY chip is connected to the magnetics &amp;#38; RJ45 on one side, and offers a normalized data interface (MII, GMII, RGMII, SGMII etc).&#034;&gt;PHY&lt;/abbr&gt;).&lt;/p&gt;
&lt;p&gt;This setup allows to practically measure with great precision the achieved
latency in realistic conditions (including the delays in the Marvell Gigabit PHYs).
The results were extremely close to our simulations.&lt;/p&gt;
&lt;div class='spip_document_38 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;18&#034; data-legende-lenx=&#034;&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='https://www.alse-fr.com/sites/alse-fr.com/IMG/jpg/tower.jpg' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/jpeg&#034;&gt; &lt;img src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH667/tower-7f982.jpg?1782755774' width='500' height='667' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-38 '&gt;&lt;strong&gt;Tower of DE2-115
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;&lt;h2 class=&#034;spip&#034;&gt;Complementary tools&lt;/h2&gt;
&lt;p&gt;We have developed an &#8220;Embedded Sniffer&#8221; : a special version of the Master
forwards all (or some) circulating frames to another (3&lt;sup class=&#034;typo_exposants&#034;&gt;rd&lt;/sup&gt;) Ethernet port for
analysis with a PC using Wireshark, without disturbing the Ring network.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;Conclusion&lt;/h2&gt;
&lt;p&gt;Our technology (based on an optimized ultra-low latency Gigabit Ethernet cut-through switch) can enable a new range of industrial applications that were not feasible so far.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_ps'&gt;&lt;p&gt;If your system consists of several boards that need to communicate
with each other and exchange data with very small delays and latency,
our technology may help you.
Do not hesitate to &lt;a href='https://www.alse-fr.com/Contact.html' class=&#034;spip_in&#034;&gt;Contact us&lt;/a&gt;&lt;/p&gt;&lt;/div&gt;
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