<?xml 
version="1.0" encoding="utf-8"?><?xml-stylesheet title="XSL formatting" type="text/xsl" href="https://www.alse-fr.com/spip.php?page=backend.xslt" ?>
<rss version="2.0" 
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:atom="http://www.w3.org/2005/Atom"
>

<channel xml:lang="en">
	<title>A.L.S.E the FPGA Experts</title>
	<link>https://www.alse-fr.com/</link>
	<description>A.L.S.E: Advanced Logic Synthesis for Electronics, offers a complete range of Services, IPs, Training courses and Boards to help you with the design of FPGA-based and EmbeddedSystems.</description>
	<language>en</language>
	<generator>SPIP - www.spip.net</generator>
	<atom:link href="https://www.alse-fr.com/spip.php?id_rubrique=41&amp;page=backend" rel="self" type="application/rss+xml" />

	<image>
		<title>A.L.S.E the FPGA Experts</title>
		<url>https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L144xH42/siteon0-d414d.png?1672825095</url>
		<link>https://www.alse-fr.com/</link>
		<height>42</height>
		<width>144</width>
	</image>



<item xml:lang="en">
		<title>Floating Points in FPGAs</title>
		<link>https://www.alse-fr.com/Floating-Points-in-FPGAs.html</link>
		<guid isPermaLink="true">https://www.alse-fr.com/Floating-Points-in-FPGAs.html</guid>
		<dc:date>2024-02-28T10:58:01Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="https://www.alse-fr.com/sites/alse-fr.com/IMG/logo/ieee754-2.jpg" length="116782" type="image/jpeg" />



		<description>
&lt;p&gt;Are you tempted about using Floating Point vectors (&#8220;Reals&#8221;) in your next FPGA project ? Can this be done ? How ? Is it a good idea ? Then this Application Note (an extract from our FPGA Design Training course) is for you&#8230;&lt;/p&gt;


-
&lt;a href="https://www.alse-fr.com/-Application-Notes-.html" rel="directory"&gt;Application Notes&lt;/a&gt;


		</description>


 <content:encoded>&lt;img src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH60/ieee754-2-bf454.jpg?1712328678' class='spip_logo spip_logo_right' width='150' height='60' alt=&#034;&#034; /&gt;
		&lt;div class='rss_chapo'&gt;&lt;p&gt;Are you tempted about using Floating Point vectors (&#8220;Reals&#8221;) in your next &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; project ?
Can this be done ? How ?
Is it a good idea ?&lt;/p&gt;
&lt;p&gt;Then this Application Note (an extract from our FPGA Design Training course) is for you&#8230;&lt;/p&gt;&lt;/div&gt;
		
		</content:encoded>


		
		<enclosure url="https://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/floatingpoints_apnote-2.pdf" length="435881" type="application/pdf" />
		

	</item>
<item xml:lang="en">
		<title>UARTs &amp; RS232</title>
		<link>https://www.alse-fr.com/UARTs-RS232.html</link>
		<guid isPermaLink="true">https://www.alse-fr.com/UARTs-RS232.html</guid>
		<dc:date>2024-02-13T11:57:34Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="https://www.alse-fr.com/sites/alse-fr.com/IMG/logo/rs232_scope1920.jpg" length="89588" type="image/jpeg" />



		<description>
&lt;p&gt;In 2024, some may consider that UARTs (and RS232) are a thing of the past. They couldn't be more wrong ! An RS232 link is the simplest way to exchange any kind of information between to points ! From the simplest microprocessors to the most complex Systems On Chips and Embedded processors, all have at least one UART. This is a fundamental means to monitor and debug a system. And, good news ! * A UART is very simple to design in an FPGA. * It is a very small block easy to add in a (&#8230;)&lt;/p&gt;


-
&lt;a href="https://www.alse-fr.com/-Application-Notes-.html" rel="directory"&gt;Application Notes&lt;/a&gt;


		</description>


 <content:encoded>&lt;img src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH53/rs232_scope1920-2d95f.jpg?1712328678' class='spip_logo spip_logo_right' width='150' height='53' alt=&#034;&#034; /&gt;
		&lt;div class='rss_texte'&gt;&lt;p&gt;In 2024, some may consider that UARTs (and RS232) are a thing of the past.&lt;br class='manualbr' /&gt;They couldn't be more wrong !&lt;/p&gt;
&lt;p&gt;An RS232 link is the simplest way to exchange any kind of information between to points ! From the simplest microprocessors to the most complex Systems On Chips and Embedded processors, all have at least one UART. This is a fundamental means to monitor and debug a system.&lt;/p&gt;
&lt;p&gt;And, good news ! &lt;br class='manualbr' /&gt;* A UART is very simple to design in an &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt;.&lt;br class='manualbr' /&gt;* It is a very small block easy to add in a nearly full FPGA.&lt;br class='manualbr' /&gt;* It can run at very high speeds, easily at 1 Mega bauds.&lt;/p&gt;
&lt;p&gt;This Application Note will teach all you need to know from the low level physical protocol to the designing your own UART in any FPGA !&lt;/p&gt;
&lt;div class='spip_document_197 spip_document spip_documents spip_document_file spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len=&#034;26&#034; data-legende-lenx=&#034;&#034;
&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt;
&lt;a href='https://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/an_rs232-2.pdf' class=&#034; spip_doc_lien&#034; title='PDF - 167.3 KiB' type=&#034;application/pdf&#034;&gt;&lt;img src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L64xH64/pdf-b8aed.svg?1704727328' width='64' height='64' alt='' /&gt;&lt;/a&gt;
&lt;figcaption class='spip_doc_legende'&gt; &lt;div class='spip_doc_titre crayon document-titre-197 '&gt;&lt;strong&gt;RS232 &amp; UARTs Basics
&lt;/strong&gt;&lt;/div&gt; &lt;/figcaption&gt;&lt;/figure&gt;
&lt;/div&gt;&lt;/div&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>Using the LT24 / ILI9341</title>
		<link>https://www.alse-fr.com/Using-the-LT24-ILI9341.html</link>
		<guid isPermaLink="true">https://www.alse-fr.com/Using-the-LT24-ILI9341.html</guid>
		<dc:date>2022-09-07T11:18:53Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="https://www.alse-fr.com/sites/alse-fr.com/IMG/logo/lt24.png" length="223077" type="image/png" />



		<description>
&lt;p&gt;This (2017) complete Application Note shows how to control the LT24 LCD Display from an FPGA kit. Even if you use a different LCD controller, or a different FPGA kit, you could be interested in the techniques used in this Application Note.&lt;/p&gt;


-
&lt;a href="https://www.alse-fr.com/-Application-Notes-.html" rel="directory"&gt;Application Notes&lt;/a&gt;


		</description>


 <content:encoded>&lt;img src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH41/lt24-0aaf2.png?1712387187' class='spip_logo spip_logo_right' width='150' height='41' alt=&#034;&#034; /&gt;
		&lt;div class='rss_chapo'&gt;&lt;p&gt;This (2017) complete Application Note shows how to control the LT24 LCD Display from an &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; kit.
Even if you use a different LCD controller, or a different FPGA kit, you could be interested in the techniques used in this Application Note.&lt;/p&gt;&lt;/div&gt;
		
		</content:encoded>


		
		<enclosure url="https://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/an_lt24_v2.pdf" length="462539" type="application/pdf" />
		

	</item>
<item xml:lang="en">
		<title>Gowin</title>
		<link>https://www.alse-fr.com/Gowin.html</link>
		<guid isPermaLink="true">https://www.alse-fr.com/Gowin.html</guid>
		<dc:date>2022-09-07T10:51:01Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="https://www.alse-fr.com/sites/alse-fr.com/IMG/logo/littlebee.png" length="480525" type="image/png" />



		<description>
&lt;p&gt;If you just bought the TEC0117 GOWIN LittleBee FPGA module, you can follow this small Application Note to go through the whole process of setting up the Gowin tools, creating a simple project and testing it on the FPGA board. If you don't have the board, you can still follow the step to have a view of the Gowin design flow. This small and simple Application Note was created since the available Gowin documentation is spread over many documents and videos. Note : the TEC0117 GOWIN (&#8230;)&lt;/p&gt;


-
&lt;a href="https://www.alse-fr.com/-Application-Notes-.html" rel="directory"&gt;Application Notes&lt;/a&gt;


		</description>


 <content:encoded>&lt;img src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH46/littlebee-00035.png?1712387187' class='spip_logo spip_logo_right' width='150' height='46' alt=&#034;&#034; /&gt;
		&lt;div class='rss_chapo'&gt;&lt;p&gt;If you just bought the &lt;strong&gt;TEC0117 GOWIN LittleBee &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt;&lt;/strong&gt; module, you can follow this small Application Note to go through the whole process of setting up the Gowin tools, creating a simple project and testing it on the FPGA board.&lt;br class='manualbr' /&gt;If you don't have the board, you can still follow the step to have a view of the Gowin design flow.&lt;/p&gt;&lt;/div&gt;
		&lt;div class='rss_texte'&gt;&lt;p&gt;This small and simple Application Note was created since the available Gowin documentation is spread over many documents and videos.&lt;/p&gt;
&lt;p&gt;Note : the TEC0117 GOWIN LittleBee &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; module should be available again from Trenz Electronic mid-April 2024.&lt;/p&gt;
&lt;p&gt;Whether you have the module or not, you can follow the steps to discover the Gowin FPGA design flow. This document has been update end Feb 2024.&lt;/p&gt;&lt;/div&gt;
		
		</content:encoded>


		
		<enclosure url="https://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/tec0117_apnote.pdf" length="185684" type="application/pdf" />
		

	</item>
<item xml:lang="en">
		<title>Designing for Stratix 10 &amp; Agilex FPGAs</title>
		<link>https://www.alse-fr.com/Designing-for-Stratix-10-FPGAs.html</link>
		<guid isPermaLink="true">https://www.alse-fr.com/Designing-for-Stratix-10-FPGAs.html</guid>
		<dc:date>2017-08-16T12:21:19Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		
		<enclosure url="https://www.alse-fr.com/sites/alse-fr.com/IMG/logo/agilex.png" length="263427" type="image/png" />



		<description>
&lt;p&gt;The Intel 14 nm Stratix 10, and even more the newer Intel 10 nm Agilex FPGA families offer unprecedented performance. However, taking full advantage of these architectures and associated design tools requires to adopt new design techniques and use a new generation of tools. We have the proper trainings offer to help customers. This ApNote is merely an illustration of how to achieve simply good performance with little efforts. Ultimate performance will require more efforts, but starting (&#8230;)&lt;/p&gt;


-
&lt;a href="https://www.alse-fr.com/-Application-Notes-.html" rel="directory"&gt;Application Notes&lt;/a&gt;


		</description>


 <content:encoded>&lt;img src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L150xH47/agilex-029cf.png?1672897377' class='spip_logo spip_logo_right' width='150' height='47' alt=&#034;&#034; /&gt;
		&lt;div class='rss_chapo'&gt;&lt;p&gt;The Intel 14 nm Stratix 10, and even more the newer Intel 10 nm &lt;strong&gt;Agilex &lt;/strong&gt; &lt;abbr title=&#034;Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.&#034;&gt;FPGA&lt;/abbr&gt; families offer unprecedented performance.&lt;/p&gt;
&lt;p&gt;However, taking full advantage of these architectures and associated design tools requires to adopt new design techniques and use a new generation of tools. We have the proper trainings offer to help customers.&lt;/p&gt;
&lt;p&gt;This ApNote is merely an illustration of how to achieve simply good performance with little efforts.
Ultimate performance will require more efforts, but starting from a sound design will always help.&lt;/p&gt;&lt;/div&gt;
		
		</content:encoded>


		

	</item>



</channel>

</rss>