A.L.S.E the FPGA Experts

Agilex 5 FPGAs

2024-04-27T22:56:30Z

We currently have and tested three kinds of Agilex 5 boards, shown below.

We received one of the very first Intel Kits available, thanks to our friends at Altera France.
We have several Arrow AXE5 Eagle boards on which we have ported and tested many of our IPs.
Last we got an Arrow/Trenz AXE5000 small board.

The Arrow AXE5-Eagle Development Kit

We received one of the first tested boards from the first batch produced by Trenz.

Arrow AXE5 Eagle board

We were able very quickly to test our Aurora 64B/66 IP as well as our GEDEK 10G Ethernet IP. Which both worked nicely, as expected. We also discovered some issues in the board design and it took us some efforts to use the 1G Ethernet ports !

We have also been testing the official Intel Kit (below).

The Intel-Altera Agilex 5 FPGA E-Series 065B Development Kit - Premium

Intel Agilex 5 FPGA E-Series 065B Development Kit - Premium

We were quickly excited by this expensive but high-end kit and we have used it to port and validate many of our IPs : Aurora 64B/66, 10GEDEK and JESD204B at this time.

The Intel Agilex 5 kit in action !

You can see the kit in operation in our Article about Aurora 64B/66B on Agilex 5 which comes with a Video.
If you have access to this kit, you can run the demo yourself with the programming file we provide.

The Arrow-Trenz AXE5000 kit

Arrow-Trenz AXE5000 Agilex 5 board

Thanks to our friends at Arrow France, we've got our hands on this small board soon after its release. Annoyingly, it has been produced by Trenz (Germany) but it is only sold by Arrow USA, and you'll have to pay duty fees if you buy it in Europe from Arrow USA. Maybe this has changed, check with your local Arrow agency.

We find that this kit is too small and limited in terms of connectivity and peripherals for the power of the FPGA. The price is quite contained, but you will be very limited in the projects this tiny board can host, if only by the absence of high-speed connectivity.
The CRUVI HS Connector can receive a CRUVI HS module by Trenz, but the list of available modules is also limited.

But for us, this kit was very interesting : we were able to port and test our High Performance HyperRam Controller ! Which runs flawlessly at 200 MHz with the Winbond HyperRam.

History

2024-04-27T22:08:40Z

In the beginning was Altera

ALSE has a long and strong history of three decades successfully using and supporting the Altera FPGA families and tools.

Altera Original Logo

And was an Altera Platinum Design partner and Training Center.

Altera Design Partner

Not surprisingly, we have developed over nearly 30 years a considerable know-how through hundreds of projects, many IPs, a complete Training courses portfolio, as well as many boards (which you can find in the “Boards” section).

Our Stratix V HPAPB Acquisition and Processing board was a success, and they are the core of very big Radio Astronomy instrument, listening to the universe 24/7 since 2016.

The production of our Cyclone V AVDB/Clovis board has now stopped but we have occasional requests from various parts of the world of engineers who find one and need information. The Data Sheet and User's Manual are available in AVDB's description (link above).

Then came Intel

In Dec 2015, Intel completed the acquisition of Altera.

… and ALSE became an Intel-FPGA Design Partner.

Intel FPGA Design Center

Naturally, ALSE became also an Intel-FPGA Technical Training Center with Certified Instructors.

After Altera became Intel PSG, the latest FPGA generation : Agilex 7 families were released, culminating as a concentrate of the most advanced technologies available.

It came with no surprise that designing Agilex 7 boards and taking full advantage of the FPGA capabilities represents unprecedented challenges. ALSE has been involved in several extreme Agilex 7 projects (with 400G connectivity through F-tile, R-tile PCIe Gen5, and SOC). Nothing is trivial in this kind of context. Most ALSE IPs have been ported to Agilex 7 (various tiles).

And today, it's Altera again

In March 2024, Intel announced the official launch of Altera, its new standalone FPGA company !

In 2025, Altera is no longer an Intel company.

Altera Partner

ALSE is now an Altera Solution Acceleration Partner.

Three new FPGA families came out : the high-end Agilex 9 (with embedded RF ADC/DAC capabilities), the mid-range Agilex 5 and the low range Agilex 3. See our article showing our first experiences with Agilex 5.

Floating Points

2024-02-28T07:59:20Z

Are you tempted about using Floating Point vectors (“Reals”) in your next FPGA project ?
Can this be done ? How ?
Is it a good idea ?

Then this Application Note (an extract from our FPGA Design Training course) is for you.

IPs

2024-01-02T10:45:39Z

All our IPs are available on Intel FPGAs.

AVB MILAN
Aurora 64B/66B
Aurora 8B/10B
Chip-Bridge (chip-to-chip link)
10GEDEK (10G Ethernet processor-less stack)
GEDEK (1 Gigabit/100M Ethernet processor-less stack)
Remote update (through Ethernet RS232, RS485, SPI …)
JESD204B Tx+Rx
NAND Flash Controller
HyperRam Memory Controller
PSRam Memory Controller
LPDDR Memory Controller
S/PDIF
HDMI in + HDMI out
JPEG Video Encoder + Decoder
NEW (2025) ! High-Speed JPEG Encoder
De-bayer (up to 8k 60fps)
JPEG XS Codec
Ultra-low Latency Industrial Network
and others !

You can visit our “IPs” section for more details.

High Speed LVDS communication

2023-05-13T15:20:26Z

Practically all FPGAs, even the low cost ones, offer the capability to create high-speed communication links based on LVDS signalling. If you think it's complex to use this capability, this article will prove you wrong.

LVDS (Low Voltage Differential Signalling) is a standard that uses two signals (a “pair”) to carry a value which is the (small) voltage difference between the two wires.
Typically, the voltage difference is small (0.4V eg) around a common mode voltage (1.2V eg).
LVDS pairs are terminated by a low impedance (100 Ohms eg) so each pair consumes a constant current of 3.5mA.
As a consequence, LVDS pairs can transport easily very high speed signals (above 1G) at low power, with simple and cheap wiring (twisted pairs cables, or microstrips on PCBs are typical).

Usual applications often use one pair to transport the base frequency (word) clock (50 MHz in our demo), and one or many more pairs to transport the high-speed serialized data at a factor usually between 7:1 and 10:1.

Video or image applications (like flat panel drivers or Camera links) often use a serialization factor of 7:1.
Our demo will use a 10:1 factor (500 Mbits/s).

This Application Note shows that it is very simple to create and test such a link, and we use one of the cheapest FPGA kits for this demo.

LVDS 500Mb/s demo using 2 x BeMicroMax10 boards

You can read all the details and the source code in the complete article below.

Intel Remote Update Application Note

2023-01-20T23:13:15Z

We have updated and re-published this Application Note created in 2010.
It explains the principles and implementation of multi-boot in Altera now Intel FPGAs.

The actual features available in the Intel FPGAs to allow the use of multiple configuration images in the external memory are actually far from trivial to use, and even 13 years later, the documentation remains a bit cryptic.

With practical examples in VHDL and SystemVerilog, and 6 complete projects including documented source code, for 3 different FPGA kits, including the Cyclone 10 LP family, this 17 pages document does explain in details how to add a Remote Update feature in your project.

The archive containing all the files and projects is available from a link in the Application Note, and also is also available in the resources below.

Happy Reconfiguration !

Note : the Remote Update mechanism of some more recent families (Cyclone10gx=Arria10, Stratix10 and Agilex) has changed. Even if most of the article's contents can still be applied, there are several important things which need to be modified.
If you need help on these families, contact ALSE.