A.L.S.E the FPGA Experts

SDI on Lattice

2026-07-23T15:32:01Z

The Lattice Nexus platform offers a combination of advantages that allow these FPGAs to address efficiently a number of difficult applications, especially in the small footprint + low power + low cost constraints.

We have successfully ported our SDI to this platform and addressed a challenging application.

For a customer's project, we had to design an interface between an SDI color camera and a battery-powered system we designed for an IR sensor, fitting inside a very small PCB. Some video processing also needed to fit in the FPGA, and indeed the power budget needed to be as low as possible.

We found that a Lattice CertusPro NX could be a nice fit.
But the https://en.wikipedia.org/wiki/SerDes]. _ Most recent FPGAs now offer a number of SERDESes allowing to stream data in and out of the FPGA serially at very high speeds. Moreover, recent connectivity protocols like PCIExpress, HDMI, DisplayPort etc make use of SERDESes.">SERDES Supported Standards table (page 55) doesn't include SDI.
After exchanging and getting help from the Lattice Engineering team, we had very good hopes and we decided to port and test our SDI IP on the CertusProNx.

The port went well : all our tests have passed with flying colors, and this bridge runs at a very low power. This FPGA and our IPs were an efficient combination to solve a challenging problem and offer a lot of flexibility.

We will demonstrate this IP on our future ALSE CertusProNx Development kit that will be announced and available in September.

Aurora on Avant !

2025-10-27T17:28:40Z

Discover how you can create an inter-FPGA Aurora link on the latest Lattice FPGA families.

In 2025, the Lattice Avant™ 16nm FinFET platform became available.
Taking advantage of its know-how in terms of low cost and low power consumption, Lattice now enters the mid-range FPGA market with state-of-the-art silicon.

The Avant™ families offers a faster fabric and numerous high-speed transceivers channels (up to 28 channels at 25 Gbps for the largest Avant-X) that are reaching FPGA NRZ transceiver's high boundary.

At ALSE we have a long history of working with practically all the FPGA vendors and families, and by consequence with all types of FPGA transceivers. We have developed many transceiver-based IPs including : HDMI, SDI, JESD204b, Gedek (100M/1G Ethernet), 10GEDEK (10G Ethernet), Aurora 8B/10B, and Aurora 64B/66B !

Therefore, having gained an early access to a brand new Lattice Avant-G Versa board, we could not resist to tryout this new FPGA family by porting our Aurora IPs on this platform.

In this Application Note we demonstrate a Reference Design based on our Aurora 8B/10B IP ported on the Lattice Avant families.

Note that our Aurora 64B/66B IP is also available on Avant™.
If all goes well you'll see a demo running on the Lattice booth at Embedded World.

Read our Application Note below.

MachXO5 Example Design

2025-04-27T17:57:58Z

A very long time ago, we (A.L.S.E.) have invented the concept of a processor-less Ethernet stack !
We named the IP “GEDEK” for Gigabit Ethernet Data Exchange Kit and it has since helped a lot of customers to implement high speed data transfers in their FPGA designs using minimal resources.

This Reference Design shows an application where a small FPGA (the MachXO5-25) can host 14 independent I2C controllers running in parallel, while ensuring bi-directional data transfer with a PC through Ethernet, within a fraction of the FPGA resources.

If you own the MachXO5T-NX Development Board or the MachXO5-NX Development board (Ethernet version), you can quickly test our Reference Design.

I2C & Ethernet Reference Design Principle

A Lattice MachXO5T-NX development board or MachXO5-NX development board is used with up to 4 x Pmod I2C Temperature sensors attached.
Each PMOD connector can host two sensor modules.
The design configures the sensors in their most accurate (and slowest) mode (12 bits with a resolution of 1/16^th Celsius). The sensors are read 4 times per second.

The LEDs can display the LSBits of Sensor 0 temperature, or a value written by the PC.
The LEDs are dimmed by a PWM which can be adjusted by the PC.
We provide a Python utility program : i2c_eth.py to exercise the FPGA.
We also provide a command line utility gedek_rw.exe to read and write in the FPGA register map.

The utility programs are available for Windows and Linux.

Block Diagram of the Reference Design

BlockDiagram

MachXO5T board

The commercial reference of this board is LFMXO5-100T-EVN. The documentation can be found here.

MachXO5T-NX evaluation board

MachXO5-NX board

The MachXO5™-NX Development Board, has a smaller FPGA (-25 instead of -100) and is available in two versions with and without Ethernet ! You need this reference : LFMXO5-25-E-EVN (with Ethernet support). The documentation can be found here.

MachXO5-NX board

Testing the Reference Design

All the details can be found in the document below.
You will see how to connect temperature sensors, program the board, connect it to Ethernet and interact with the board from your PC through Ethernet. You'll see how to visualize the Ethernet frames exchanged using Wireshark.

If you own a LFMXO5-100T-EVN board or a LFMXO5-25-E-EVN board, please contact us so we can send you the latest archive to test this Reference Design.

Discovering Radiant

2025-01-31T08:51:03Z

Lattice offers several families of FPGAs that are attractive for many applications.
If you want to discover and evaluate quickly the latest Lattice development tool, “Radiant”, this article will help you retrieve, install, license and use Radiant in no time, at no cost !

The document below does describe, step-by-step, how to :

Retrieve Radiant installation for Windows or Linux
Install Radiant
License Radiant (free)
Prepare your Windows or Linux environment
Launch Radiant and associated tools
Create a simple project from scratch
Compile the FPGA
Discover the main steps of the design flow
Perform simulations
Attend a free Lattice video training to dig deeper into Radiant features.

If you have some practice designing FPGAs and follow the steps, you should be able to quickly start a real-world project with Radiant.

You will find all you need in the pdf document below.

DSP in Lattice FPGAs (1)

2025-01-30T09:33:30Z

This Application note, the first of a series, demonstrates how to take advantage of the hardware resources in Lattice FPGAs to implement Digital Signal Processing functions efficiently.

We created this Application Note after having designed a dedicated and very optimized Large FIR Filter IP for a customer. We ran into issues and it took us some effort to properly use the Lattice tools and converge on an efficient methodology to take advantage of the sysDSP blocks that are available in most Lattice FPGAs.

This application note (pdf) can be downloaded below. We created also an archive (zip), which contains also the design files, the testbenches, simulation scripts and a Radiant project. You can download it from this link.

If you are not yet familiar with Radiant and would like to test the methodology described in our document, contact us to receive our “Quick Radiant Installation Guide with First Steps”.

Good reading !

LiteX and Lattice FPGAs

2024-01-04T18:39:44Z

LiteX: Enhancing FPGA development with versatility and integration

Author : Florent Kermarrec http://www.enjoy-digital.fr/

Overview of LiteX

LiteX is an FPGA framework recognized for its broad compatibility with a range of FPGA platforms, including Lattice, Intel, Xilinx and and new actors like Gowin, Efinix.

Its design philosophy centers around providing a flexible and adaptable environment for digital logic design, catering to diverse project needs.
This flexibility is amplified by its ability to integrate specialized PHYs, enabling tailored optimization for specific hardware requirements.

Application to the ColorLight Board (Lattice ECP5)

The ColorLight board, sold without schematics/FPGA pinout, posed an interesting challenge in understanding and utilizing its FPGA IOs as a regular development board.

Colorlight board

Utilizing LiteX's Python-friendly capabilities, a bitstream was developed to stream the names of the IOs directly through each corresponding pin.
This approach allowed for quick and accurate identification of the FPGA's IOs using basic equipment like an oscilloscope or UART, thereby streamlining the documentation process.

The result was a more accessible and comprehensively documented ColorLight board, enhancing its usability within the LiteX ecosystem and LiteX-Boards.

The ColorLite Example: LiteX and LiteEth Integration

The ColorLite example Design showcases the practical application of LiteX in conjunction with LiteEth for advanced networking and control functionalities.

This implementation uses LiteEth to establish Etherbone connectivity over UDP, enabling efficient peripheral control on the FPGA remotely from C or Python scripts.

This setup exemplifies how LiteX can be utilized to develop communication protocols and SoC designs, offering a versatile platform for FPGA applications.

Thoughts and Future Directions

LiteX positions itself as a tool that not only simplifies FPGA development but also encourages innovation through its capacity for integration and collaboration.
Its compatibility with various FPGA families and the ability to work alongside proprietary solutions, such as Gedek by ALSE, highlights the complementary nature of different approaches in the FPGA community.

The growing trend of open-source projects, much like what we've seen in software development, suggests a future filled with joint efforts and significant advancements in FPGA design and technology!

Remote Update for Lattice FPGAs

2023-04-27T17:56:36Z

ALSE has ported its GEDEK IP and the Remote Update option to the Lattice families. You will find here a step-by-step User Guide showing the principles and how to use this IP in your Lattice FPGA projects.

July 2026 : our Remote Update IP is now available on the Lattice Nexus Platform ! (CertusProNx, CroslinkNx, MachXO5 etc).

If you are not familiar with the GEDEK IP, follow this link.

The document below describes all the details on using the Remote Update option of the ALSE Gigabit Ethernet IP to allow you to safely update your Lattice FPGA board(s) through Ethernet, remotely.

To demonstrate the concept and its implementation, we use a very cheap and widely available Board : the Chinese Colorlight 5A-75B board, which implements a Lattice ECP5 FPGA with a Winbond 25Q32JVSIQ 32 Mbits SPI Flash. Its low price made it very popular to the open source and enthusiasts communities.
This board has very few inputs (one button !) but the ECP5 FPGA is quite powerful with 25k LEs, and there are two Gigabit Ethernet ports (we use one in this application) and an external Ram (that we don't use).

In this project, we will not use any processor core either, but a simple project which consists essentially in the instantiation of our GEDEK IP with its Remote Update option. The complete design uses a fraction of the FPGA (around 14%) and provides the complete bi-directional Gigabit Ethernet communication feature (capable of loss-less transfer of 2 x 113 Mbytes/s), and indeed the capability to update remotely the memory through Ethernet !

The files archive can be downloaded from here.

The full article is available below.