What is IO Checker ?

2024-03-14T17:18:01Z

If you are involved with designing a board with an FPGA on it, starting with the schematics and ending in a functional PCB, then this article is four you !

Rationale

Today more than ever, doing things quickly and right the first time is critical in any project.

For HDL and Digital Design, we have created efficient training courses that help achieving rapid success through rigorous coding and a robust Methodology.

But when it comes to schematics and PCB layout, the situation is much more complex.
One of the issue is the complexity of modern FPGAs (with hundreds or thousands of pins to assign, with a lot of different power supplies, and with electrical standards and pin out constraints that are extremely difficult to manage).
Indeed, there are many other issues (from creating valid hardware to anticipating signal integrity issues) but the task of managing power supply nets and creating all the pin assignments in general is often underestimated… until it needs to be performed !

In any case, nobody wants to receive a batch of prototypes to discover the FPGA is not usable due to incorrect pin assignments ! Do you plan for the cost (and delay) of a complex PCB respin ?

A big helper

We have discovered and we use now IO Checker, from HDL Works. It removes the frustration of long, painful, and error-prone task of assigning all the pins between the schematics and the FPGA tools, including the pins that don't show in the source code (Supplies, Grounds, NC, Programming, JTag, Special purposes, external memories, etc). IO Checker knows the purpose of all the pins of your FPGA !

We can help you verify your schematics, but we think it's better if you can handle this yourself, especially to optimize your iterations, reduce your schematics and FPGA design time, and make sure the transition to the PCB will be smooth and without error.

See for yourself

On the HDL Works website, you will find the IO Checker section and this Introduction video which clearly presents IO Checker.

You'll find another video showing how to create, verify and maintain the pin assignment constraints.

Take a look at the videos !

Practical Example

We have the plan to write an Application Note showing how we used IO Checker to verify a very complex Agilex 7 board. Stay tuned.

A.L.S.E the FPGA Experts

What is IO Checker ?

Rationale

A big helper

See for yourself

Practical Example