Assertions Based Verification

2024-07-18T23:00:07Z

If you don't use Assertions yet, think twice !
You are lagging behind and you miss a huge opportunity to create better code, to enhance your verification, to find bugs faster and to make your life more interesting.

Assertion-Based Verification is an old and proven methodology, compulsory in ASIC projects, which is also leading the industry (as the entry language for formal tools).

Good news ! It will take you a single (intensive) day to be properly trained !

Introduction

We have created a condensed and intensive Training, delivered either in one long day or two half-days, which does teach how to take advantage of the Property Specification Language “PSL” for Assertion-Based Verification.

PSL is an IEEE standard (1850) now integrated in the VHDL language.
SystemVerilog includes the SVA syntax that implements the same concepts, so moving from PSL to SVA or vice-versa is very easy.

Last but not least, PSL (like SVA) is now supported by most of the simulators proposed by the FPGA vendors (QuestaSim OEM Editions), even in their free (“Starter”) version. No more excuse !

ABV : Why ?

Adopting the Assertions Based Verification (ABV) methodology is the easiest and cheapest investment you can make to increase drastically the quality of your designs and to reduce both the verification efforts and time-to-market.

Since very long ago, ABV has been compulsory for ASIC and IPs, but the FPGA community has been lagging behind and has not yet adopted widely advanced verification methods. FPGA Engineers not being correctly trained and lack of support by many simulators were among the reasons. There is no excuse today !

At every step in a project, from the specification to RTL coding, to unitary testing, to debugging, to functional coverage, and to certification when applicable, ABV will help you. Both the Design and the Verification teams must take advantage of ABV.

Cherry on the cake : PSL is the entry language of formal tools ! We can expect that the FPGA community will gradually adopt formal tools (like the ASIC design community did), and we start seeing open-source formal tools.

ABV : How ?

Our intensive and short training will give you the keys of ABV. It teaches PSL in depth, which is the Assertions language used by VHDL users. (SystemVerilog users have the SVA syntax).

The training starts by teaching the ABV methodology and how to reap its benefits.
It does indeed cover in details all the syntax available, including advanced constructs.

The key value of this training is the five practical and progressive exercises supervised by the instructor. Without them, the actual learning doesn't really happen.

Who should attend ?

System Architects and any person involved in specifying digital systems. PSL allows to create exact (unambiguous) and executable specifications !
Digital Designers (RTL coding and unitary verification) will boost their productivity.
Verification engineers will experience a breakthrough in efficiency.
Team leaders in charge of enforcing better design practices and methodology.

Objectives

Understand the principles and benefits of ABV.
Master completely PSL IEEE 1850 Language and Features.
Practice PSL through many exercises and examples.
Acquire the correct methodology and use ABV optimally.

Properties and PSL in the design and verification flow.
Using Properties in directed testing, constrained random testing and static formal verification.
Syntax & semantic of the PSL language with its different layers (boolean, temporal, …)
Writing properties and avoiding common pitfalls and errors.
Exercising PSL properties and assertions with a simulator
Taking advantage of PSL to collect easily invaluable functional coverage information.
How to use PSL and ABV wisely to maximize the ROI.

Pre-requisites

You must master VHDL, know how to write test benches and how to use a simulator.

Course material

Based on the original material from Doulos, ALSE has assembled a dense and efficient contents that can fit in a single training day (or be delivered in two “half-days”).

Participants will receive :

The main Training Course Manual in pdf, which constitutes a PSL Reference Manual.
An exercise Workbook in pdf (to print before the course).
An archive containing the files for the exercises and some reference material.
An access in the cloud to the industry simulators: Siemens QuestaSim, Cadence Xcelium, Synopsys VCS, and Aldec. The free version of QuestaSim OEM edition can also be used locally. Note that GHDL has a partial support of PSL.
As an option : a printed copy of the « PSL Golden Reference Guide » from Doulos.

If you are interested by this training please contact ALSE now !

A.L.S.E the FPGA Experts