These rules and coding style are the result of more than 23 years of HDL design and teaching experience, hundreds of complex ASIC & FPGA projects, hundreds of thousands of lines of code, and the development of a very rich portfolio of complex IPs.
This Coding Guide is “reasonable”: small and simple enough to be easily remembered, “no-nonense” in that only useful rules have been kept. However it is covering a lot of the usual mistakes and it can significantly enhance the quality of the VHDL code.
It is probably useful to remind at this stage that :
- Following the rules is not sufficient per se: this Coding Guide is in no way teaching the fundamental principles that any HDL designer must master to create efficient and reliably working designs.
It is the purpose of our Training Courses !
- The other way around is also true: some of these rules can be bent while a correct, working, design is achieved, if there is a good understanding of the potential issues that may result.
- The Naming Conventions proposed here are not absolute rules. You may decide to adopt other naming conventions, but it is not acceptable to not have any naming convention enforced at all!
In summary, this document is only proposing a number of recommendations that, if followed, will reduce the design risks and globally augment the code quality and reliability.
These Coding Rules are copyright ALSE. If you want to reproduce them or use them by any means, you must contact ALSE and request an authorization. However, strictly personal use is allowed.
Obtaining the full document
You can view the complete Guide using the link below.