Aurora 8B/10B IP Core

Aurora 8B/10B is an open, lightweight, high-speed, and low latency serial protocol suitable for chip-to-chip, board-to-board and backplane applications using Transceivers.
For AMD/Xilinx users, Aurora 8B/10B is available through the Xilinx Logicore IP for some FPGA families, but not all (in which case we can help) !
The ALSE Aurora 8B/10B IP Core makes Aurora 8B/10B available to all FPGAs (and potentially ASICs), including all Altera FPGAs with transceivers (Cyclone, Arria, Stratix, Agilex 3/5/7/9), Lattice FPGAs (CertusPro Nx, Avant-X, Avant-G), Microchip FPGAs (PolarFire, RTG4) and Efinix (Titanium).
Therefore, this IP provides an efficient way to interconnect an AMD/Xilinx FPGA (for example) with an FPGA from another vendor. Complete interoperability with the Xilinx IP is guaranteed.
It can also be used to interconnect two FPGAs from the same vendor together, in replacement of other proprietary or complex High-Speed Serial protocols (like Serial Lite IV or PCIExpress).
Or indeed two FPGAs from any vendor!
The Figure below shows a typical application of the ALSE AUrora 8B/10B IP linking an FPGA with an AMD FPGA:

Aurora Typical Application

Back to OverviewAll Aurora 8B/10B Protocol Features are supported including :

  • Full-Duplex, Simplex Tx and Simplex Rx Operation supported
  • Currently demonstrated at up to 6.6 Gbps (Gigabits per seconds) per Transceiver lane.
    Higher bitrates are possible, depending on the Device Transceiver characteristics (max 8b/10b Encoder/Decoder Bitrate).
  • Up to 16 Transceiver lanes.
  • Framing and Streaming interface.
  • Payload Data User Frames (PDU)
  • User Flow Control (UFC).
  • Native Flow Control (NFC), in immediate and completion mode.
  • Additional CRC for PDU Frames
  • 8b/10b Encoding / Decoding.
  • Clock Compensation sequence generation.
  • Per lane polarity inversion and skew compensation.
  • User datapath depending on number of lanes and 16bits/32bits mode per Transceiver lane. Examples :
    -> in a x1 /32bits configuration, the user datapath is 32bits.
    -> in a x4 /16bits configuration, the user datapath is 64bits.
    -> in a x4 /32bits configuration, the user datapath is 128bits.

Note : we have also an Aurora 64B/66B IP core available for higher speeds !

Back to OverviewOther Technical Features

  • All Altera FPGAs (with transceivers) are supported. _We support also other FPGA vendors (including Lattice, Microsemi/Microchip and Efinix).
  • AXI streaming / Avalon-ST compatible for User interfaces (PDU, NFC, UFC)
  • Very low FPGA resource usage : typically less than 1000 ALMs / 2 Memory Blocks for a Full IP in a x1 (1 lane) configuration
  • Provided with SDC Timing Constraints and QIP file for easy integration in Platform Designer.
  • Hardware Tester Reference Designs

Back to OverviewExamples of existing Hardware Tester Reference Designs

Altera (Intel) :

  • Agilex 7 kits
  • Agilex 5 Eagle kit
  • Cyclone 10 GX dev kit
  • Arria10 Attila (ReflexCES)
  • Arria10 Achilles (ReflexCES)
  • Stratix10 GX Dev Kit
  • Cyclone V Clovis/AVDB
  • Cyclone V Clovis/AVDB

Lattice :

  • Avant G & Avant-X Versa boards
  • CertusPro Nx Evaluation board
  • CertusPro-NX Versa Board See our article and its Application Note.

Efinix :

  • Efinix Titanium development kit

Microchip :

  • Microchip Polarfire MPF300T development kit
  • and more …

Back to Overview

Document download

Back to top