Synchronous SRAM (SSRAM) Controller

No Bus Latency / No Wait Memories support

Low Latency is often very important in many fields such as cache-based products, broadcast, networking and communications applications, video streaming / video games, etc …
Synchronous SRAM memories are very good candidates for such latency-sensitive applications, thanks to their (very) low latency (typically one clock cycle), high performance.
Interfacing such memories to an FPGA is easy using to the optimized ALSE controller. Thanks to its very small FPGA footprint and low resource usage, this controller fits in the smallest FPGAs, which makes it also perfect for the Automotive and Consumer Markets.

Main Technical Features

  • High-Performance Controller supporting Burst Mode for Read/Write transfers, to get optimized transfer speed and minimal switch fabric overhead.
  • Memory Operating Frequency typically up to 133 MHz, depending on FPGA and Memory speed grades, and (more marginally) on the customer PCB characteristics.
  • 32bits Slave Interface (Avalon-MM based) with Burst support. Typically, the Controller will serve a Master that can be an Altera Nios II CPU (32bits), with or without caches, with or without Burst mode. A hardware master (DMA) is of course also possible (e.g : Video streaming DMAs, etc …)
  • Specific version of the controller for No Bus Latency memories, also called Zero Wait States memories (such as ISSI IS61NLF204836B / IS61NLF409618B, or Cypress CY7C1471BV33 / CY7C1473BV33), for 100% bandwidth utilization (no dead cycles)
  • Very low FPGA resource usage : less than 200 Logic Cells, and two memory blocks
  • Versatile : This IP can be used in all FPGA devices (Intel / Altera, Xilinx, Lattice, MicroSemi / Actel) having internal memory blocks.
  • Provided with sophisticated SDC Timing Constraints, Hardware Tester Reference Designs, etc…

Typical waveforms

SSRAM no bus latency waveform - JPEG - 196.3 kb
SSRAM no bus latency waveform

Here is above a typical waveform of consecutive Read/Write accesses, with/without bursts, with Zero Wait state (no bus latency) and thus 100% bandwidth utilization. The clock can be up to 133 MHz here.

Examples of supported Memories

  • ISSI IS61LPS25632B
  • ISSI IS61NLF204836B/IS61NLF409618B
  • Cypress CY7C1471BV33 / CY7C1473BV33
  • etc …