Main Technical Features
- High-Performance Controller
- Supports NAND Flash Asynchronous Timing Mode from 0 (slowest) to 5 (fastest).
- Supports 2KB, or 4KB or 8KB NAND page size, and latest (at time of writing) NAND memory densities : 32Gbits, 64Gbits, 128Gbits, etc…
- Supports 4 bytes or 5 bytes NAND Address Command.
Support of multiple Dies (CE#) Flash memories.
- Ability to control the NAND Flash with or without the use of the RDY/BUSY NAND Flash pin.
- 32bits Bi-directional Embedded DMA Engine (Avalon-MM) from/to User Logic, with Burst Mode support for optimized transfer speed and minimal switch fabric overhead, and Interrupts generation at end of operation (Erase/Program/Read) to minimize CPU overhead.
- 32 bits Registers Slave Interface (Avalon-MM) for Control.
Typically, the Controller will serve a Master that can be for example an Altera Nios II CPU, an ARM-A9 HPS, another embedded CPU, or no CPU at all (processor-less applications, full hardware solution).
- Ability to read the NAND Status Register for high-level Bad Block detection and Management, and status of any other operation.
Error Check & Correct
- Automatic & Transparent Error Check and Correct. The ECC is based on BCH algorithm, 8 bits correction for 540 bytes of Data).
Please contact ALSE for other ECC schemes. Simpler ECC Hamming code (1 bit correction) is also available, for smaller FPGA resource usage.
- Additional data checking using 32-bits CRC for even better performance and smaller read latency.
This IP can be used in all FPGA devices (Altera, Xilinx, Lattice, Actel/MicroSemi). However, internal memory blocks must be available, so CPLDs like Altera MaxII & MaxV are not supported.
- Can be integrated seamlessly using Altera Qsys tool, or manually. It is maintained up-to-date with the latest version of the FPGA tools (older versions on request).
- Compact. With ECC BCH enabled (8bits correction), the area is typically around 4,000 Logic Elements, and 10 to 20 memory blocks (M9K) are used (depending the NAND Page Size). With ECC Hamming (1bit correction) enabled, the area is typically less than 1,500 Logic Elements, and 4 to 10 memory blocks are used.
- Provided with sophisticated SDC Timing Constraints, for easy IP integration.
- Provided with a Hardware or Software Reference Design, an example API, etc… ALSE can optionally test the controller on your custom FPGA board before delivering the IP.
- First-class English/French Technical Support (E-mail and Telephone, extended CET hours).
Example of NAND Flash Memories supported :
- Micron MT29F4G08ABADAWP_nand
- Micron MT29F32G08ABAAAWP
- Micron MT29F128G08AJAAAWP
Please contact ALSE for other NAND Flash models.