This core is designed to add an HDMI input to an FPGA, only requiring a connector (and optionally an ESD protection circuit to protect the FPGA.
Indeed, it requires the use of 4 x SERDESes in the FPGA.
Note that we do not implement HDCP (contents protection by encryption).
Easy to use
Our core is compact and implements standard interfaces, so it can be used easily either as a standalone block, or as part of a Qsys system. It does not require an embedded processor.
This core is small and efficient enough to fit easily in a low cost and small FPGA, like in the Intel Cyclone V family.
Main Technical characteristics
- Video formats supported :
- HD-ready (720p)
- Full-HD (1080p)
- UHD (2160p), 24 bits per pixel (16M colors)
- Decodes main auxiliary packets such as Auxiliary Video Information, Audio InfoFrame, General Control Packet, HDMI Vendor-Specific InfoFrame
- Receives video and audio (L-PCM)
- Transmits main auxiliary packets such as Auxiliary Video Information, Audio InfoFrame, General Control Packet, HDMI Vendor-Specific InfoFrame
- Output interface :
- Avalon ST-Video
- Avalon ST for audio stream (user packet)
- Parallel Interface (Vsync, Hsync, Data Enable)
this allows using this core easily with Qsys and the Altera Video IP suite (“VIP”).
- Implements an user-editable EDID table.
Other settings and adapting the IP core to specific demands can be available upon request.
Demos are available
- on Arria 10 (Attila kit from Reflex with FMC HDMI Daughter Card from Bitec) : Full-HD and UHD Formats.
This IP is one of the few that cannot be simply demonstrated on our AVDB Video Dev Kit (because we have a raw DisplayPort input, and the HDMI input uses an Aanlog Device Decoder chip).
Contact us if you want more details.