Aurora 64B/66B IP Core

Aurora 64B/66B is a lightweight and open protocol suitable for chip-to-chip, board-to-board and backplane applications using very high speed transceivers.

The ALSE Aurora 64B/66B IP core is a very compact and optimized but exhaustive implementation of this protocol, also developed and verified to ensure full compatibility with the Xilinx IP core (interoperability has been tested and demonstrated).

This IP is available on all the high-end Altera/Intel FPGAs (from Stratix V and Cyclone10gx to Agilex 3/5/7/9), but also for all other FPGA vendors including Lattice, Microchip and Efinix.

Last but not least, we have developed and delivered an ASIC version of our Aurora 64B/66B IP !

Compared to the 8B/10B version of the Aurora protocol, the 64B/66B flavor does address the highest lanes speeds (when 8B/10B typically stops at 6 GBs per lane).
It also offers an effective bandwidth of up to 97%, instead of 80% for 8B/10B.

Our Aurora64B/66B IP therefore provides an efficient way to interconnect Altera/Intel, AMD/Xilinx, Lattice, Microsemi/Microchip and Efinix FPGAs, or any other chip (ASIC, ASSP, etc …) using the public Aurora 64B/66B protocol.

Typical application

Back to Overviewour IP supports all the Aurora-Protocol Features including :

  • Full implementation of Aurora protocol
  • Up to 16 lanes
  • Full-Duplex, Simplex Tx and Simplex Rx modes.
  • 64-bits user datapath
  • Framing and Streaming interfaces
  • Up to 16 transceiver lanes per Aurora instance
  • User K-block interface
  • Native Flow Control
  • User Flow Control
  • Additional CRC for PDU frames
  • Clock compensation
  • Complete Interoperability with Xilinx Aurora 64 core
  • Per lane polarity inversion and skew compensation.
  • AXI and Avalon-ST Streaming compatible.
  • and much more…

Back to OverviewArchitecture

Aurora64 Architecture

Back to OverviewExamples of Reference Designs platforms

Altera :

  • Agilex 7 kits
  • Agilex 5 Arrow Eagle kit
  • Agilex 5 Altera kit
  • Cyclone 10 GX dev kit
  • Arria10 Attila (ReflexCES)
  • Arria10 Achilles (ReflexCES)
  • Stratix10 GX Dev Kit
  • Cyclone V Clovis/AVDB
  • Cyclone V Clovis/AVDB
  • and many other boards…

Lattice :

  • Avant-G & Avant-X Versa boards
  • CertusPro Nx Evaluation board
  • CertusPro-NX Versa Board

Efinix :

  • Efinix Titanium development kit

Microchip :

  • Microchip Polarfire MPF300T development kit
  • and more …

Back to OverviewAgilex 5 <-> Ultrascale+ 50G Demo

This demo is built using our Aurora 64B/66B Reference Design. Here is the architecture :

Demo Architecture

Note : if you don’t have a Xilinx kit, you can run the demo on the Agilex5 kit with a QSFP+ loopback module.

The Guide to run the demo is here :

ALSE Aurora64 Agilex5 Demo User Guide

.

You can see the video here.

The programming (and probing) files are available here :

Demo_Agi5_devkit_2026
Agilex 5 kit programming and probing files

Back to OverviewExamples of tested Aurora configurations - (not exhaustive !)

The table below shows tested configurations connecting a Xilinx-AMD FPGA and IP to an Altera FPGA through the ALSE Aurora IP. This demonstrates the interoperability between the IPs and FPGAs.

The table below shows some examples of ALSE Aurora 64 IP on Microchip FPGAs connected to Xilinx-AMD FPGAs.

Examples of ALSE Aurora 64 IP on Microchip FPGAs

The table below shows some examples of ALSE Aurora 64 IP on Lattice FPGAs connected to Xilinx-AMD FPGAs.

Examples of ALSE Aurora 64 IP on Lattice FPGAs

We have a similar tables for Efinix (Titanium) FPGAs.

Back to Overview

Document download

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