Quad SPI Controller

For an FPGA-based project, replacing bulky, pin-consuming, and complex Parallel Flash Memories by modern Quad-SPI Flash devices is very exciting in many respects.
It drastically reduces the FPGA pin count and thus enables smaller (and cheaper) packages. It also reduces the power consumption, minimizes the PCB area & complexity, reduces the BOM, while providing good transfer speed, etc…

The major issue against Quad SPI memories is that Parallel Flash Memories are usually much simpler to interface with, and may even not require any specific controller (though this is less and less true).

At A.L.S.E, we have taken into account this growing demand and we have developed an extremely efficient and compact (yet affordable) Quad-SPI Controller, which has already been adopted by many customers, especially in the very demanding and competitive field of Automotive Equipment Manufacturers.

Main Technical Features

  • High-Performance Controller !
    In some applications, we have seen boot time reduction by a factor of more than 20x !
  • Supports Burst Mode transfers for optimized transfer speed and minimal switch fabric overhead.
  • Takes fully advantage of the multi-lanes (x4) capability.
  • Transfer speed up to 52MBytes/s (Quad SPI clock up to 104 MHz) or more, depending on FPGA and QSPI Memory type and speed grades.
  • Quad IO Programming (x4) is also supported

Versatile

  • This IP can be used in all FPGA Altera devices (including MAX / MAXII families, since no memory blocks are needed in some configurations). For other FPGA vendors (Xilinx, Lattice, MicroSemi/Actel), please contact ALSE.
  • We support most Flash Vendors & types (Winbond, Spansion, Numonyx, Micron…).
  • Support the latest densities, like 256MBits/512MBits/1Gbits (4 bytes-address mode)
  • Includes Clock Domain Crossing Management for best area and transfer speed results.
  • Special “Direct Command Mode” available to access Quad SPI low-levels commands directly from the Avalon Master interface, allowing memory specific operations as Lock/Unlock, Read of Status Registers, Flash ID, Software Reset, etc …
  • Support of the additional QSPI Hardware Reset pin for Flash supporting it
  • Multi-chip management. An option allows to parallel two QSPI Flash devices (with an extra CS signal) to double the storage space. Ask ALSE for this.
  • Modular: Embedded programming can be activated or deactivated, for security reason or for area minimization purpose. FIFO depths can be easily adapted regarding customer FPGA constraints.

Simple Interface

  • 32bits Slave Interface (Avalon-MM) with Burst support.
    Typically, the Controller will serve a Master that can be an Altera Nios II CPU (32bits), with or without Caches, with or without Burst mode.

A hardware master is of course also possible so this controller can also be used without an embedded processor.

Compact !

  • The area can be trimmed down to less than 600-700 Logic Elements, and even 0 (zero) internal memory block.
  • Partial Transparent CFI Flash Emulation (a very special feature developed by ALSE), designed and optimized to be compliant with Altera nios2-flash-programmer. This option greatly facilitates the adoption of the Quad-SPI as a replacement of standard CFI Parallel Flash memories (programming is essentially the same as for Parallel Flash devices).
  • Easy integration in Altera Qsys or manually (no processor in system)
  • Delivered with sophisticated SDC Timing Constraints, and Hardware/Software Reference Designs, etc…

Device Support

Examples of supported Quad-SPI Memories :

  • Spansion / Cypress S25FL129P, S25FL512, etc …
  • Micron M25Q256 etc…
  • Macronix 25L256 etc…
  • Winbond W25Q80, W25Q16, W25Q32, etc …
  • Numonyx N25Q256, N25Q512, etc …
  • etc …

Even if your specific Flash is not supported (to be verified), ALSE could easily add it to the list.

Document download