This core is designed to add an HDMI output to an FPGA, only requiring a connector (and optionally a re-driver to isolate the FPGA and enhance the transmission strength).
It requires the use of 4 x SERDESes in the FPGA.
Note that we do not implement HDCP (contents protection by encryption).
Easy to use
Our core is compact and implements standard interfaces, so it can be used easily either as a standalone block, or as part of a Qsys system. It does not require an embedded processor.
This core is small and efficient enough to fit easily in a low cost and small FPGA, like in the Intel Cyclone V family.
This IP core is used in most Reference Designs that are available with ALSE’s AVDB Video board. In many cases, purchasing an AVDB board to develop or to prototype the application will make a lot of sense.
Main Technical characteristics
- Video formats supported :
- HD-ready (720p)
- Full-HD (1080p)
- UHD (2160p), 24 bits per pixel (16M colors)
- The core handles 1 pixel per clock cycle for 720p and 1080p formats, and 4 pixels per clock cycle for UHD.
- Supports different color spaces : RGB / 4:4:4 / 4:2:2 / 4:2:0 for 2160p60 or 2160p50
- Includes video timings for following :
- 2160p50* / 2160p60* (* : in 4:2:0 only)
- Transmits video and audio (L-PCM)
- Transmits main auxiliary packets such as Auxiliary Video Information, Audio InfoFrame, General Control Packet, HDMI Vendor-Specific InfoFrame
- Input interface : Avalon Video-ST (also for audio stream)
this allows using this core easily with Qsys and the Altera Video IP suite (“VIP”).
- Implements an user-editable EDID table.
Other settings and adapting the IP core to specific demands can be available upon request.
Demos are available
- on Cyclone V (AVDB) : HD-Ready-720p / Full-HD-1080p / UHD-2160p
- on Arria 10 (Attila kit from Reflex with FMC HDMI Daughter Card from Bitec) : Full-HD and UHD Formats.
Contact us if you want more details.