Copy Protection

Inadequate design security is emerging as one of the single largest threats to the intellectual-property-based economies of the modern world.
Consequences of inadequate design security can include lost revenue due to counterfeit products and increased liability due to product tampering.

ALSE has developed a low-cost yet efficient FPGA Copy Protection system.

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Introduction

Copy protection issues usually do not concern ASIC designers, but most SRAM-based FPGA designers must keep in mind that unauthorized parties can very easily: over-build, copy, clone and re-use their precious bitstream. Some FPGA vendors offer now specific families that implement internal protection schemes, but :

  • Vendors protections are often cracked
  • These protections are not available to all FPGAs anyway

So the simple solution developed by ALSE and described here can be suitable in many cases.

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ALSE solution

As a response to this copy protection challenge, ALSE has designed a cost-effective fixed-secret authentication scheme based on a cheap and secure authentication device. The authentication is achieved through a variable challenge-response mechanism and user secret keys. Communication with the host is implemented through a single wire interface, in order to avoid consuming precious I/Os, and to simplify the board layout.

The solution is based on an external Authentication Component which embeds the same crypto engine. It can be fitted in most secure and inexpensive CPLDs, like Altera’s MaxII EPM240 (eg) or other small devices. For quantities and depending on the device selected, the cost could be in the 1 $ per unit range.

AntiCopy
AntiCopy
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Security Achieved

In spite of its compactness, the protection includes many layers and features that complicate cracking and prevent usual known methods to be used.

So, while not offering monetary-grade security, this protection is still adequate enough for protecting most industrial applications.

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Discover more in our document: CPLD-based Anti-Copy Protection.

Remember:

Design Protection = < 400 FPGA Logic Cells + 1 wire + 1 $ + ALSE IP.

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